#1
\intbl{\b S1}\cell{Input}\cell\row
\intbl{\b S2}\cell{Input coordinate}\cell\row
\intbl{\b S3}\cell{Output coordinate S2}\cell\row
\intbl{\b S4}\cell{Input coordinate}\cell\row
\intbl{\b S5}\cell{Output coordinate S4}\cell\row
\intbl{\b S6}\cell{Input coordinate}\cell\row
\intbl{\b S7}\cell{Output coordinate S6}\cell\row
\intbl{\b S8}\cell{Input coordinate}\cell\row
\intbl{\b S9}\cell{Output coordinate S8}\cell\row
\intbl{\b S10}\cell{Input coordinate}\cell\row
\intbl{\b S11}\cell{Output coordinate S10}\cell\row
\intbl{\b S12}\cell{Input coordinate}\cell\row
\intbl{\b S13}\cell{Output coordinate S12}\cell\row
\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is piecewise linearly interpolated function of input}\cell\row\par
#2
\intbl{\b S1}\cell{Output value}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output equals input (a constant)}\cell\row\par
#3
\intbl{\b S1}\cell{Input}\cell\row
\intbl{\b S2}\cell{Track switch (0=track 1=release)}\cell\row
\intbl{\b S3}\cell{Time constant T1 (lead) sec}\cell\row
\intbl{\b S4}\cell{Time constant T2 (lag) sec}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output follows input with lead or lag applied}\cell\row\par
#4
\intbl{\b S1}\cell{Setpoint signal}\cell\row
\intbl{\b S2}\cell{Feedback signal}\cell\row
\intbl{\b S3}\cell{Forward stroke rate (%/sec)}\cell\row
\intbl{\b S4}\cell{Reverse stroke rate (%/sec)}\cell\row
\intbl{\b S5}\cell{Deadband (percent)}\cell\row
\intbl{\b S6}\cell{Cycle time (sec)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is duration of increase pulse (positive increment)}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is duration of decrease pulse (negative increment)}\cell\row\par
#5
\intbl{\b S1}\cell{Input signal (units/sec)}\cell\row
\intbl{\b S2}\cell{Scaling parameter - units/pulse}\cell\row
\intbl{\b S3}\cell{Low cutoff}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N }\cell{Bit}\cell{Output is pulsed with frequency proportional to input value}\cell\row\par
#6
\intbl{\b S1}\cell{Input}\cell\row
\intbl{\b S2}\cell{High limit value}\cell\row
\intbl{\b S3}\cell{Low limit value}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output follows input, but is always between the limits}\cell\row\par
#7
\intbl{\b S1}\cell{Input}\cell\row
\intbl{\b S2}\cell{Gain parameter of input}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output equals gain times square root of input}\cell\row\par
#8
\intbl{\b S1}\cell{Input}\cell\row
\intbl{\b S2}\cell{Track switch (0=track 1=release)}\cell\row
\intbl{\b S3}\cell{Increase rate limit (1/sec)}\cell\row
\intbl{\b S4}\cell{Decrease rate limit (1/sec)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output follows input, with maximum rate limit.}\cell\row\par
#9
\intbl{\b S1}\cell{Input 1}\cell\row
\intbl{\b S2}\cell{Input 2}\cell\row
\intbl{\b S3}\cell{Transfer signal (0=S1 1=S2)}\cell\row
\intbl{\b S4}\cell{Time constant transfer to input 1}\cell\row
\intbl{\b S5}\cell{Time constant transfer to input 2}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is selected from the two inputs.}\cell\row\par
#10
\intbl{\b S1}\cell{Input 1}\cell\row
\intbl{\b S2}\cell{Input 2}\cell\row
\intbl{\b S3}\cell{Input 3}\cell\row
\intbl{\b S4}\cell{Input 4}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is highest of the four inputs}\cell\row\par
#11
\intbl{\b S1}\cell{Input 1}\cell\row
\intbl{\b S2}\cell{Input 2}\cell\row
\intbl{\b S3}\cell{Input 3}\cell\row
\intbl{\b S4}\cell{Input 4}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is lowest of the four inputs}\cell\row\par
#12
\intbl{\b S1}\cell{Input}\cell\row
\intbl{\b S2}\cell{Value of alarm point / high limit}\cell\row
\intbl{\b S3}\cell{Value of alarm point / low limit}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{High alarm: output indicates input is greater than or equal to high limit}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Low alarm: output indicates input is less than or equal to low limit}\cell\row\par
#13
\intbl{\b S1}\cell{Input 1}\cell\row
\intbl{\b S2}\cell{Input 2}\cell\row
\intbl{\b S3}\cell{Transfer signal (0=S1 1=S2)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Integer}\cell{Output is selected from the two (integer) inputs}\cell\row\par
#14
\intbl{\b S1}\cell{Input 1}\cell\row
\intbl{\b S2}\cell{Input 2}\cell\row
\intbl{\b S3}\cell{Input 3}\cell\row
\intbl{\b S4}\cell{Input 4}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is sum of the four input signals}\cell\row\par
#15
\intbl{\b S1}\cell{Input 1}\cell\row
\intbl{\b S2}\cell{Input 2}\cell\row
\intbl{\b S3}\cell{Gain parameter of input 1}\cell\row
\intbl{\b S4}\cell{Gain parameter of input 2}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is weighted sum of the two input signals.}\cell\row\par
#16
\intbl{\b S1}\cell{Input 1}\cell\row
\intbl{\b S2}\cell{Input 2}\cell\row
\intbl{\b S3}\cell{Gain parameter}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is weighted product of the two input signals}\cell\row\par
#17
\intbl{\b S1}\cell{Input 1}\cell\row
\intbl{\b S2}\cell{Input 2}\cell\row
\intbl{\b S3}\cell{Output gain}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is weighted quotient of the two input signals}\cell\row\par
#18
\intbl{\b S1}\cell{Error signal}\cell\row
\intbl{\b S2}\cell{Spare}\cell\row
\intbl{\b S3}\cell{Track reference signal}\cell\row
\intbl{\b S4}\cell{Track switch signal (0=track 1=release)}\cell\row
\intbl{\b S5}\cell{(K) gain multiplier}\cell\row
\intbl{\b S6}\cell{(KP) proportional constant}\cell\row
\intbl{\b S7}\cell{(KI) integration constant (1/minute)}\cell\row
\intbl{\b S8}\cell{(KD) derivative constant (minute)}\cell\row
\intbl{\b S9}\cell{High output limit}\cell\row
\intbl{\b S10}\cell{Low output limit}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is PID signal}\cell\row\par
#19
\intbl{\b S1}\cell{Process value}\cell\row
\intbl{\b S2}\cell{Setpoint}\cell\row
\intbl{\b S3}\cell{Track reference signal}\cell\row
\intbl{\b S4}\cell{Track switch signal (0=track 1=release)}\cell\row
\intbl{\b S5}\cell{(K) gain multiplier}\cell\row
\intbl{\b S6}\cell{(KP) proportional constant}\cell\row
\intbl{\b S7}\cell{(KI) integration constant (1/minute)}\cell\row
\intbl{\b S8}\cell{(KD) derivative constant (minute)}\cell\row
\intbl{\b S9}\cell{High output limit}\cell\row
\intbl{\b S10}\cell{Low output limit}\cell\row
\intbl{\b S11}\cell{0=normal 1=integral only (KI.ne.0) setpoint change}\cell\row
\intbl{\b S12}\cell{0=reverse acting 1=direct acting on error}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is PID signal}\cell\row\par
#20
\intbl{\b S1}\cell{Input 1}\cell\row
\intbl{\b S2}\cell{Input 2}\cell\row
\intbl{\b S3}\cell{Input 3}\cell\row
\intbl{\b S4}\cell{Indicator station address (8-11)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Integer}\cell{No output}\cell\row\par
#21
\intbl{\b S1}\cell{Process value}\cell\row
\intbl{\b S2}\cell{Setpoint track value}\cell\row
\intbl{\b S3}\cell{Automatic signal}\cell\row
\intbl{\b S4}\cell{Control output track signal}\cell\row
\intbl{\b S5}\cell{Track switch (TS) 1=track 0=norm}\cell\row
\intbl{\b S6}\cell{Manual interlock (1=manual 0=release)}\cell\row
\intbl{\b S7}\cell{Process value high alarm point in engineering units}\cell\row
\intbl{\b S8}\cell{Process value low alarm point in engineering units}\cell\row
\intbl{\b S9}\cell{Process value/setpoint deviation alarm}\cell\row
\intbl{\b S10}\cell{Process value/setpoint signal span in engineering units}\cell\row
\intbl{\b S11}\cell{Process value zero value in engineering units}\cell\row
\intbl{\b S12}\cell{Setpoint zero value in engineering units}\cell\row
\intbl{\b S13}\cell{Engineering units ID (OIU use only)}\cell\row
\intbl{\b S14}\cell{Setpoint track option 0=no 1=process value 2=S2 3=S2/manual+auto}\cell\row
\intbl{\b S15}\cell{Computer backup 0=hold 1=manual 2=auto}\cell\row
\intbl{\b S16}\cell{DCS address (>15 no station)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Control output in percent}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Setpoint in engineering units}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Control mode: 0 - manual, 1 - automatic}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Control state: 0 - local, 1 - computer}\cell\row
\intbl{\b N+4}\cell{Bit}\cell{Station mode: always 0}\cell\row
\intbl{\b N+5}\cell{Bit}\cell{Computer time-out: 0 - no, 1 - yes}\cell\row\par
#22
\intbl{\b S1}\cell{Process value}\cell\row
\intbl{\b S2}\cell{Cascade input}\cell\row
\intbl{\b S3}\cell{Automatic signal}\cell\row
\intbl{\b S4}\cell{Control output track signal (track)}\cell\row
\intbl{\b S5}\cell{Track switch (TS) 1=track 0=norm}\cell\row
\intbl{\b S6}\cell{Manual interlock (1=manual)}\cell\row
\intbl{\b S7}\cell{Process value high alarm point in engineering units}\cell\row
\intbl{\b S8}\cell{Process value low alarm point in engineering units}\cell\row
\intbl{\b S9}\cell{Process value/setpoint deviation alarm}\cell\row
\intbl{\b S10}\cell{Process value/setpoint signal span in engineering units}\cell\row
\intbl{\b S11}\cell{Process value zero value in engineering units}\cell\row
\intbl{\b S12}\cell{Setpoint zero value in engineering units}\cell\row
\intbl{\b S13}\cell{Engineering units ID (OIU use only)}\cell\row
\intbl{\b S14}\cell{Setpoint track option (0=no 1=process value 2=cascade 3=cascade always)}\cell\row
\intbl{\b S15}\cell{Computer backup 0=hold 1=manual 2=auto 3=cascade}\cell\row
\intbl{\b S16}\cell{DCS address (>15 no station)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Control output in percent}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Setpoint in engineering units}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Control mode: 0 - manual, 1 - automatic}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Control state: 0 - local, 1 - computer}\cell\row
\intbl{\b N+4}\cell{Bit}\cell{Station mode: 0 - BASIC, 1 - cascade}\cell\row
\intbl{\b N+5}\cell{Bit}\cell{Computer time-out: 0 - no, 1 - yes}\cell\row\par
#23
\intbl{\b S1}\cell{Process value}\cell\row
\intbl{\b S2}\cell{Uncontrolled (wild) variable}\cell\row
\intbl{\b S3}\cell{Automatic signal}\cell\row
\intbl{\b S4}\cell{Control output track signal}\cell\row
\intbl{\b S5}\cell{Track switch (TS) 1=track 0=norm}\cell\row
\intbl{\b S6}\cell{Manual interlock (1=manual)}\cell\row
\intbl{\b S7}\cell{Process value high alarm point in engineering units}\cell\row
\intbl{\b S8}\cell{Process value low alarm point in engineering units}\cell\row
\intbl{\b S9}\cell{Process value/setpoint deviation alarm}\cell\row
\intbl{\b S10}\cell{Process value/setpoint signal span in engineering units}\cell\row
\intbl{\b S11}\cell{Process value zero value in engineering units}\cell\row
\intbl{\b S12}\cell{Setpoint zero value in engineering units}\cell\row
\intbl{\b S13}\cell{Engineering units ID (OIU use only)}\cell\row
\intbl{\b S14}\cell{Setpoint track option 0=no 1=process value 2=S2 3=S2/manual+auto}\cell\row
\intbl{\b S15}\cell{Computer backup 0=hold 1=manual 2=auto 3=ratio}\cell\row
\intbl{\b S16}\cell{DCS address (>15 no station)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Control output in percent}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Setpoint in engineering units}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Control mode: 0 - manual, 1 - automatic}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Control state: 0 - local, 1 - computer}\cell\row
\intbl{\b N+4}\cell{Bit}\cell{Station mode: 0 - BASIC, 1 - ratio}\cell\row
\intbl{\b N+5}\cell{Bit}\cell{Computer time-out: 0 - no, 1 - yes}\cell\row\par
#24
\intbl{\b S1}\cell{Input}\cell\row
\intbl{\b S2}\cell{Block number containing specification to be adapted}\cell\row
\intbl{\b S3}\cell{Specification to be adapted}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{N/A}\cell{Not used}\cell\row\par
#25
\intbl{\b S1}\cell{Requested module address}\cell\row
\intbl{\b S2}\cell{Requested block address}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output value with quality. Quality: 0 - good, 1 - bad}\cell\row\par
#26
\intbl{\b S1}\cell{Requested module address}\cell\row
\intbl{\b S2}\cell{Requested block address}\cell\row
\intbl{\b S3}\cell{Requested PCU address}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is analog input value}\cell\row\par
#27
\intbl{\b S1}\cell{Signal zero in engineering units}\cell\row
\intbl{\b S2}\cell{Signal span in engineering units}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 201}\cell{Real}\cell{Fixed analog input 1 with quality}\cell\row
\intbl{\b 202}\cell{Real}\cell{Fixed analog input 2 with quality}\cell\row
\intbl{\b 203}\cell{Real}\cell{Fixed analog input 3 with quality}\cell\row
\intbl{\b 204}\cell{Real}\cell{Fixed analog input 4 with quality}\cell\row\par
#28
\intbl{\b S1}\cell{Destination module address}\cell\row
\intbl{\b S2}\cell{Destination block address}\cell\row
\intbl{\b S3}\cell{Input}\cell\row
\intbl{\b S4}\cell{Engineering units zero of input}\cell\row
\intbl{\b S5}\cell{Engineering units span of input}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is transmitted value with quality}\cell\row\par
#29
\intbl{\b S1}\cell{Input}\cell\row
\intbl{\b S2}\cell{Station block associated with output}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 211}\cell{Real}\cell{Fixed analog output 1}\cell\row
\intbl{\b 212}\cell{Real}\cell{Fixed analog output 2}\cell\row\par
#30
\intbl{\b S1}\cell{Input}\cell\row
\intbl{\b S2}\cell{Engineering units ID}\cell\row
\intbl{\b S3}\cell{Engineering units zero of input (S1)}\cell\row
\intbl{\b S4}\cell{Engineering units span of input (S1)}\cell\row
\intbl{\b S5}\cell{High alarm limit value}\cell\row
\intbl{\b S6}\cell{Low alarm limit value}\cell\row
\intbl{\b S7}\cell{Significant change (percent of span)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Analog output value with quality}\cell\row\par
#31
\intbl{\b S1}\cell{Input 1}\cell\row
\intbl{\b S2}\cell{Input 2}\cell\row
\intbl{\b S3}\cell{Input 3}\cell\row
\intbl{\b S4}\cell{Input 4}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is point quality: 0 - all inputs good, 1 - at least 1 input bad}\cell\row\par
#32
\intbl{\b S1}\cell{Input}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is module status: 0 - normal operation, 1 - module disabled}\cell\row\par
#33
\intbl{\b S1}\cell{Input}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is logical inverse of input}\cell\row\par
#34
\intbl{\b S1}\cell{Set input}\cell\row
\intbl{\b S2}\cell{Reset input}\cell\row
\intbl{\b S3}\cell{Initial state}\cell\row
\intbl{\b S4}\cell{Override value(0=reset 1=set)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is set/reset flip flop function of inputs}\cell\row\par
#35
\intbl{\b S1}\cell{Input}\cell\row
\intbl{\b S2}\cell{0=pulse output 1=timed out 2=timing}\cell\row
\intbl{\b S3}\cell{Time delay (in sec)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is the logic state of the input using either a timed out, timing, or gated pulse function to determine the state.}\cell\row\par
#36
\intbl{\b S1}\cell{Input 1}\cell\row
\intbl{\b S2}\cell{Input 2}\cell\row
\intbl{\b S3}\cell{Input 3}\cell\row
\intbl{\b S4}\cell{Input 4}\cell\row
\intbl{\b S5}\cell{Input 5}\cell\row
\intbl{\b S6}\cell{Input 6}\cell\row
\intbl{\b S7}\cell{Input 7}\cell\row
\intbl{\b S8}\cell{Input 8}\cell\row
\intbl{\b S9}\cell{Number of outputs that must be logical 1}\cell\row
\intbl{\b S10}\cell{Select test (0 - must equal or exceed S9, 1 - must equal S9}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is a counted logical OR of the inputs}\cell\row\par
#37
\intbl{\b S1}\cell{Input 1}\cell\row
\intbl{\b S2}\cell{Input 2}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is logical AND of inputs}\cell\row\par
#38
\intbl{\b S1}\cell{Input 1}\cell\row
\intbl{\b S2}\cell{Input 2}\cell\row
\intbl{\b S3}\cell{Input 3}\cell\row
\intbl{\b S4}\cell{Input 4}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is logical AND of inputs}\cell\row\par
#39
\intbl{\b S1}\cell{Input 1}\cell\row
\intbl{\b S2}\cell{Input 2}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is logical OR of inputs}\cell\row\par
#40
\intbl{\b S1}\cell{Input 1}\cell\row
\intbl{\b S2}\cell{Input 2}\cell\row
\intbl{\b S3}\cell{Input 3}\cell\row
\intbl{\b S4}\cell{Input 4}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is logical OR of inputs}\cell\row\par
#41
\intbl{\b S1}\cell{Requested module address}\cell\row
\intbl{\b S2}\cell{Requested block address}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is digital input value}\cell\row\par
#42
\intbl{\b S1}\cell{Requested module address}\cell\row
\intbl{\b S2}\cell{Requested block address}\cell\row
\intbl{\b S3}\cell{Requested PCU address}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is digital input value with quality}\cell\row\par
#43
\intbl{\b S1}\cell{Input: 0=logic 0 normally closed, 1=logic 1 normally closed, 2=unused}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 221}\cell{Bit}\cell{Fixed digital input 1}\cell\row
\intbl{\b 222}\cell{Bit}\cell{Fixed digital input 2}\cell\row
\intbl{\b 223}\cell{Bit}\cell{Fixed digital input 3}\cell\row\par
#44
\intbl{\b S1}\cell{Input}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 231}\cell{Bit}\cell{Fixed digital output 1}\cell\row
\intbl{\b 232}\cell{Bit}\cell{Fixed digital output 2}\cell\row
\intbl{\b 233}\cell{Bit}\cell{Fixed digital output 3}\cell\row
\intbl{\b 234}\cell{Bit}\cell{Fixed digital output 4}\cell\row\par
#45
\intbl{\b S1}\cell{Input}\cell\row
\intbl{\b S2}\cell{Alarm state: 0=alarm is logic 0, 1=alarm is logic 1, 2=no alarm state}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is value of exception report}\cell\row\par
#46
\intbl{\b S1}\cell{Module address}\cell\row
\intbl{\b S2}\cell{Input 1}\cell\row
\intbl{\b S3}\cell{Input 2}\cell\row
\intbl{\b S4}\cell{Input 3}\cell\row
\intbl{\b S5}\cell{Input 4}\cell\row
\intbl{\b S6}\cell{Input 5}\cell\row
\intbl{\b S7}\cell{Input 6}\cell\row
\intbl{\b S8}\cell{Input 7}\cell\row
\intbl{\b S9}\cell{Input 8}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is value of S2}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Output is value of S3}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Output is value of S4}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Output is value of S5}\cell\row
\intbl{\b N+4}\cell{Bit}\cell{Output is value of S6}\cell\row
\intbl{\b N+5}\cell{Bit}\cell{Output is value of S7}\cell\row
\intbl{\b N+6}\cell{Bit}\cell{Output is value of S8}\cell\row
\intbl{\b N+7}\cell{Bit}\cell{Output is value of S9}\cell\row\par
#47
\intbl{\b S1}\cell{Type (0=linear, 1=square root) signals are 1-5V or 4-20 ma}\cell\row
\intbl{\b S2}\cell{Engineering units ID}\cell\row
\intbl{\b S3}\cell{Engineering units zero of input of S1}\cell\row
\intbl{\b S4}\cell{Engineering units span of input of S1}\cell\row
\intbl{\b S5}\cell{High alarm point limit value}\cell\row
\intbl{\b S6}\cell{Low alarm point limit value}\cell\row
\intbl{\b S7}\cell{Significant change (percent of span)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Description}\cell\row
\intbl{\b 1-8}\cell{Output is exception value of NAMMO1 internal points}\cell\row
\intbl{\b 9-16}\cell{Output is exception value of group 0 of first slave module}\cell\row
\intbl{\b 17-24}\cell{Output is exception value of group 1 of first slave module}\cell\row
\intbl{\b 25-32}\cell{Output is exception value of group 2 of second slave module}\cell\row
\intbl{\b 33-40}\cell{Output is exception value of group 3 of second slave module}\cell\row
\intbl{\b 41-48}\cell{Output is exception value of group 4 of third slave module}\cell\row
\intbl{\b 49-56}\cell{Output is exception value of group 5 of third slave module}\cell\row
\intbl{\b 57-64}\cell{Output is exception value of group 6 of fourth slave module}\cell\row
\intbl{\b 65-72}\cell{Output is exception value of group 7 of fourth slave module}\cell\row\par
#48
#49
\intbl{\b S1}\cell{Input}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is value of S1}\cell\row\par
#50
\intbl{\b S1}\cell{Output value}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is equal to S1}\cell\row\par
#51
\intbl{\b S1}\cell{Real constant specified}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is equal to S1}\cell\row\par
#52
\intbl{\b S1}\cell{Integer constant specified}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Integer}\cell{Output is equal to S1}\cell\row\par
#53
\intbl{\b S1}\cell{Exception report time units}\cell\row
\intbl{\b S2}\cell{Minimum exception report time (250 ms increments)}\cell\row
\intbl{\b S3}\cell{Maximum exception report time (250 ms increments)}\cell\row
\intbl{\b S4}\cell{Significant change parameter loop reports (percent span)}\cell\row
\intbl{\b S5}\cell{Alarm deadband high/low reports (percent span)}\cell\row
\intbl{\b S6}\cell{Alarm deadband deviation reports (percent span)}\cell\row
\intbl{\b S7}\cell{Watchdog timeout on computer communications (2.56 sec increment)}\cell\row
\intbl{\b S8}\cell{Module bus update time (same PCU) 250 ms increments)}\cell\row
\intbl{\b S9}\cell{Minimum cycle time algorithms (10 ms increments)}\cell\row
\intbl{\b S10}\cell{Configuration lock (1=lock 0=unlock)}\cell\row
\intbl{\b S11}\cell{Maximum derivative gain for PID}\cell\row
\intbl{\b S12}\cell{PID external reset option 0=normal 1=external reset}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 240}\cell{Bit}\cell{Output indicates startup in progress: 1 for first 15 seconds of module execute mode; then 0}\cell\row
\intbl{\b 241}\cell{Bit}\cell{Output indicates non-volatile RAM in initialize mode: 1 indicates switch is closed}\cell\row
\intbl{\b 242}\cell{Bit}\cell{Output indicates state of general purpose switch}\cell\row
\intbl{\b 243}\cell{Real}\cell{Output is last control cycle time}\cell\row
\intbl{\b 244}\cell{Bit}\cell{Output indicates valid time received from bus module}\cell\row
\intbl{\b 245}\cell{Real}\cell{Output is current hour (0 to 23)}\cell\row
\intbl{\b 246}\cell{Real}\cell{Output is current minutes (0 to 59)}\cell\row
\intbl{\b 247}\cell{Real}\cell{Output is current seconds (0 to 59)}\cell\row
\intbl{\b 248}\cell{Real}\cell{Output is current year (0 to 99)}\cell\row
\intbl{\b 249}\cell{Real}\cell{Output is current month (1 to 12)}\cell\row
\intbl{\b 250}\cell{Real}\cell{Output is current day (1 to 31)}\cell\row
\intbl{\b 251}\cell{Real}\cell{Output is current day of week: Sunday = 1, etc.}\cell\row
\intbl{\b 252}\cell{Real}\cell{Output is revision level}\cell\row
\intbl{\b 253}\cell{Real}\cell{Output is non-volatile RAM utilization factor}\cell\row
\intbl{\b 254}\cell{Real}\cell{Output is RAM utilization factor}\cell\row\par
#54
\intbl{\b S1}\cell{Configuration lock (1=lock 0=unlock)}\cell\row
\intbl{\b S2}\cell{Module bus update time (specified in 10ms increments)}\cell\row
\intbl{\b S3}\cell{Minimum blocks 4-127}\cell\row
\intbl{\b S4}\cell{Maximum blocks 4-127}\cell\row
\intbl{\b S5}\cell{Minimum blocks 128-135}\cell\row
\intbl{\b S6}\cell{Maximum blocks 128-135}\cell\row
\intbl{\b S7}\cell{Minimum blocks 136-143}\cell\row
\intbl{\b S8}\cell{Maximum blocks 136-143}\cell\row
\intbl{\b S9}\cell{Minimum blocks 144-151}\cell\row
\intbl{\b S10}\cell{Maximum blocks 144-151}\cell\row
\intbl{\b S11}\cell{Minimum blocks 152-159}\cell\row
\intbl{\b S12}\cell{Maximum blocks 152-159}\cell\row
\intbl{\b S13}\cell{Minimum blocks 160-167}\cell\row
\intbl{\b S14}\cell{Maximum blocks 160-167}\cell\row
\intbl{\b S15}\cell{Minimum blocks 168-175}\cell\row
\intbl{\b S16}\cell{Maximum blocks 168-175}\cell\row
\intbl{\b S17}\cell{Minimum blocks 176-183}\cell\row
\intbl{\b S18}\cell{Maximum blocks 176-183}\cell\row
\intbl{\b S19}\cell{Minimum blocks 184-191}\cell\row
\intbl{\b S20}\cell{Maximum blocks 184-191}\cell\row
\intbl{\b S21}\cell{Minimum blocks 192-199}\cell\row
\intbl{\b S22}\cell{Maximum blocks 192-199}\cell\row
\intbl{\b S23}\cell{Minimum blocks 200-207}\cell\row
\intbl{\b S24}\cell{Maximum blocks 200-207}\cell\row
\intbl{\b S25}\cell{Minimum blocks 208-215}\cell\row
\intbl{\b S26}\cell{Maximum blocks 208-215}\cell\row
\intbl{\b S27}\cell{Minimum blocks 216-223}\cell\row
\intbl{\b S28}\cell{Maximum blocks 216-223}\cell\row
\intbl{\b S29}\cell{Minimum blocks 224-231}\cell\row
\intbl{\b S30}\cell{Maximum blocks 224-231}\cell\row
\intbl{\b S31}\cell{Minimum blocks 232-239}\cell\row
\intbl{\b S32}\cell{Maximum blocks 232-239}\cell\row
\intbl{\b S33}\cell{Minimum blocks 240-247}\cell\row
\intbl{\b S34}\cell{Maximum blocks 240-247}\cell\row
\intbl{\b S35}\cell{Minimum blocks 248-255}\cell\row
\intbl{\b S36}\cell{Maximum blocks 248-255}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 2}\cell{None}\cell{No output}\cell\row\par
#55
\intbl{\b S1}\cell{Slave address}\cell\row
\intbl{\b S2}\cell{Output device select}\cell\row
\intbl{\b S3}\cell{LVDT select}\cell\row
\intbl{\b S4}\cell{Output action on LVDT error}\cell\row
\intbl{\b S5}\cell{LVDT frequency select in khz}\cell\row
\intbl{\b S6}\cell{Percent position demand}\cell\row
\intbl{\b S7}\cell{LVDT null check mode select}\cell\row
\intbl{\b S8}\cell{Calibration stroke time}\cell\row
\intbl{\b S9}\cell{Calibration cycle count}\cell\row
\intbl{\b S10}\cell{Calibration type}\cell\row
\intbl{\b S11}\cell{Calibrate mode enable}\cell\row
\intbl{\b S12}\cell{Calibrate go/hold select}\cell\row
\intbl{\b S13}\cell{Hard manual mode select}\cell\row
\intbl{\b S14}\cell{Spare boolean input}\cell\row
\intbl{\b S15}\cell{Block output display units}\cell\row
\intbl{\b S16}\cell{Demodulator gain constant}\cell\row
\intbl{\b S17}\cell{Controller gain proportional constant}\cell\row
\intbl{\b S18}\cell{LVDT 1 differential voltage at 0% position}\cell\row
\intbl{\b S19}\cell{LVDT 1 differential voltage at 100% position}\cell\row
\intbl{\b S20}\cell{LVDT 2 differential voltage at 0% position}\cell\row
\intbl{\b S21}\cell{LVDT 2 differential voltage at 100% position}\cell\row
\intbl{\b S22}\cell{Contingency deadband in percent}\cell\row
\intbl{\b S23}\cell{Spare real parameter}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is percent or volts actuator position with quality}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output indicates IMHSS03 D/A converter output with quality}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output indicates servo 1 coil 1 output current with quality}\cell\row
\intbl{\b N+3}\cell{Real}\cell{Output indicates servo 1 coil 2 output current with quality}\cell\row
\intbl{\b N+4}\cell{Real}\cell{Output indicates servo 2 coil 1 output current with quality}\cell\row
\intbl{\b N+5}\cell{Real}\cell{Output indicates servo 2 coil 2 output current with quality}\cell\row
\intbl{\b N+6}\cell{Real}\cell{Output indicates module status}\cell\row
\intbl{\b N+7}\cell{Real}\cell{Output indicates LVDT status}\cell\row
\intbl{\b N+8}\cell{Bit}\cell{Output indicates module hardware status: 0 - good, 1 - bad}\cell\row
\intbl{\b N+9}\cell{Bit}\cell{Output indicates module communication and watchdog timer status: 0 - good, 1 - bad}\cell\row
#56
\intbl{\b S1}\cell{Configuration lock (1=lock 0=unlock)}\cell\row
\intbl{\b S2}\cell{Alarm deadband high/low reports (percent span)}\cell\row
\intbl{\b S3}\cell{Minimum blocks 1-8}\cell\row
\intbl{\b S4}\cell{Maximum blocks 1-8}\cell\row
\intbl{\b S5}\cell{Minimum blocks 9-16}\cell\row
\intbl{\b S6}\cell{Maximum blocks 9-16}\cell\row
\intbl{\b S7}\cell{Minimum blocks 17-24}\cell\row
\intbl{\b S8}\cell{Maximum blocks 17-24}\cell\row
\intbl{\b S9}\cell{Minimum blocks 25-32}\cell\row
\intbl{\b S10}\cell{Maximum blocks 25-32}\cell\row
\intbl{\b S11}\cell{Minimum blocks 33-40}\cell\row
\intbl{\b S12}\cell{Maximum blocks 33-40}\cell\row
\intbl{\b S13}\cell{Minimum blocks 41-48}\cell\row
\intbl{\b S14}\cell{Maximum blocks 41-48}\cell\row
\intbl{\b S15}\cell{Minimum blocks 49-56}\cell\row
\intbl{\b S16}\cell{Maximum blocks 49-56}\cell\row
\intbl{\b S17}\cell{Minimum blocks 57-64}\cell\row
\intbl{\b S18}\cell{Maximum blocks 57-64}\cell\row
\intbl{\b S19}\cell{Minimum blocks 65-72}\cell\row
\intbl{\b S20}\cell{Maximum blocks 65-72}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 75}\cell{None}\cell{No output}\cell\row\par
#57
\intbl{\b S1}\cell{Reserved for future use}\cell\row
\intbl{\b S2}\cell{Number of bytes of memory required}\cell\row
\intbl{\b S3}\cell{Reserved for future use}\cell\row
\intbl{\b S4}\cell{Reserved for future use}\cell\row
\intbl{\b S5}\cell{Reserved for future use}\cell\row
\intbl{\b S6}\cell{Reserved for future use}\cell\row
\intbl{\b S7}\cell{Reserved for future use}\cell\row
\intbl{\b S8}\cell{Maximum number of Harmony Area Controllers}\cell\row
\intbl{\b S9}\cell{Reserved for future use}\cell\row
\intbl{\b S10}\cell{Reserved for future use}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 31999}\cell{Real}\cell{Options configuration}\cell\row
\intbl{\b 32000}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 32001}\cell{Real}\cell{Output indicates total number of bytes transmitted by the node per second}\cell\row
\intbl{\b 32002}\cell{Real}\cell{Output indicates total number of messages transmitted by the node per second}\cell\row
\intbl{\b 32003}\cell{Real}\cell{Output indicates total number of bytes received by the node per second}\cell\row
\intbl{\b 32004}\cell{Real}\cell{Output indicates total number of bytes sent by the node per second}\cell\row
\intbl{\b 32005}\cell{Real}\cell{Output indicates total number of messages received by the node per second}\cell\row
\intbl{\b 32006}\cell{Real}\cell{Output indicates total number of messages sent by the node per second}\cell\row
\intbl{\b 32007}\cell{Real}\cell{Output indicates total number of exception reports received by the node per second}\cell\row
\intbl{\b 32008}\cell{Real}\cell{Output indicates total number of exception reports sent by the node per second}\cell\row
\intbl{\b 32009}\cell{Real}\cell{Output indicates total number of GMI messages received by the node per second}\cell\row
\intbl{\b 32010}\cell{Real}\cell{Output indicates total number of GMI messages sent by the node per second}\cell\row
\intbl{\b 32011}\cell{Real}\cell{Output indicates percentage of module processing power of node currently being used}\cell\row
\intbl{\b 32012}\cell{Real}\cell{Output indicates total number of bytes transferred on the expander bus to the NIO from the communications module per second}\cell\row
\intbl{\b 32013}\cell{Real}\cell{Output indicates total number of bytes transferred on the expander bus from the NIO to the communications module per second}\cell\row
\intbl{\b 32014}\cell{Real}\cell{Output indicates total number of messages transferred on the expander bus to the NIO from the communications module per second}\cell\row
\intbl{\b 32015}\cell{Real}\cell{Output indicates total number of messages transferred on the expander bus from the NIO to the communications module per second}\cell\row
\intbl{\b 32016}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 32017}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 32018}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 32019}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 32020}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 32021}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 32022}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 32023}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 32024}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 32025}\cell{Real}\cell{Reserved}\cell\row
\par
#58
\intbl{\b S1}\cell{Input X}\cell\row
\intbl{\b S2}\cell{Rate input (rate in units/sec)}\cell\row
\intbl{\b S3}\cell{Track switch signal (0=track 1=release)}\cell\row
\intbl{\b S4}\cell{Length of queue (length in units)}\cell\row
\intbl{\b S5}\cell{Number of intervals (N)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is time delayed value of input}\cell\row\par
#59
\intbl{\b S1}\cell{Input 1}\cell\row
\intbl{\b S2}\cell{Input 2}\cell\row
\intbl{\b S3}\cell{Transfer switch (0=input 1 1=input 2)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is value of selected input}\cell\row\par
#60
\intbl{\b S1}\cell{Blocks 128-135}\cell\row
\intbl{\b S2}\cell{Blocks 136-143}\cell\row
\intbl{\b S3}\cell{Blocks 144-151}\cell\row
\intbl{\b S4}\cell{Blocks 152-159}\cell\row
\intbl{\b S5}\cell{Blocks 160-167}\cell\row
\intbl{\b S6}\cell{Blocks 168-175}\cell\row
\intbl{\b S7}\cell{Blocks 176-183}\cell\row
\intbl{\b S8}\cell{Blocks 184-191}\cell\row
\intbl{\b S9}\cell{Blocks 192-199}\cell\row
\intbl{\b S10}\cell{Blocks 200-207}\cell\row
\intbl{\b S11}\cell{Blocks 208-215}\cell\row
\intbl{\b S12}\cell{Blocks 216-223}\cell\row
\intbl{\b S13}\cell{Blocks 224-231}\cell\row
\intbl{\b S14}\cell{Blocks 232-239}\cell\row
\intbl{\b S15}\cell{Blocks 240-247}\cell\row
\intbl{\b S16}\cell{Blocks 248-255}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx1400\cellx2320\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 128-255}\cell{Bit}\cell{Output indicates value: 0 - open circuit, 1 - closed circuit}\cell\row\par
#61
\intbl{\b S1}\cell{Input 1}\cell\row
\intbl{\b S2}\cell{Input 2}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output blinks at a constant rate}\cell\row\par
#62
\intbl{\b S1}\cell{Set signal}\cell\row
\intbl{\b S2}\cell{Set permissive signal}\cell\row
\intbl{\b S3}\cell{Reset signal}\cell\row
\intbl{\b S4}\cell{Override signal}\cell\row
\intbl{\b S5}\cell{Initialize signal}\cell\row
\intbl{\b S6}\cell{Feedback signal}\cell\row
\intbl{\b S7}\cell{Alarm signal}\cell\row
\intbl{\b S8}\cell{Type parameter (for OIU)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is set/reset flip flop function of inputs}\cell\row\par
#63
\intbl{\b S1}\cell{Update period (250 msec increments)}\cell\row
\intbl{\b S2}\cell{Module address}\cell\row
\intbl{\b S3}\cell{Input 1}\cell\row
\intbl{\b S4}\cell{Input 2}\cell\row
\intbl{\b S5}\cell{Input 3}\cell\row
\intbl{\b S6}\cell{Input 4}\cell\row
\intbl{\b S7}\cell{Input 5}\cell\row
\intbl{\b S8}\cell{Input 6}\cell\row
\intbl{\b S9}\cell{Input 7}\cell\row
\intbl{\b S10}\cell{Input 8}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is value of S3}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is value of S4}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is value of S5}\cell\row
\intbl{\b N+3}\cell{Real}\cell{Output is value of S6}\cell\row
\intbl{\b N+4}\cell{Real}\cell{Output is value of S7}\cell\row
\intbl{\b N+5}\cell{Real}\cell{Output is value of S8}\cell\row
\intbl{\b N+6}\cell{Real}\cell{Output is value of S9}\cell\row
\intbl{\b N+7}\cell{Real}\cell{Output is value of S10}\cell\row\par
#64
\intbl{\b S1}\cell{Update period (250 msec increments)}\cell\row
\intbl{\b S2}\cell{Module address}\cell\row
\intbl{\b S3}\cell{Input 1}\cell\row
\intbl{\b S4}\cell{Input 2}\cell\row
\intbl{\b S5}\cell{Input 3}\cell\row
\intbl{\b S6}\cell{Input 4}\cell\row
\intbl{\b S7}\cell{Input 5}\cell\row
\intbl{\b S8}\cell{Input 6}\cell\row
\intbl{\b S9}\cell{Input 7}\cell\row
\intbl{\b S10}\cell{Input 8}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is value of S3}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Output is value of S4}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Output is value of S5}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Output is value of S6}\cell\row
\intbl{\b N+4}\cell{Bit}\cell{Output is value of S7}\cell\row
\intbl{\b N+5}\cell{Bit}\cell{Output is value of S8}\cell\row
\intbl{\b N+6}\cell{Bit}\cell{Output is value of S9}\cell\row
\intbl{\b N+7}\cell{Bit}\cell{Output is value of S10}\cell\row\par
#65
\intbl{\b S1}\cell{Input 1}\cell\row
\intbl{\b S2}\cell{Input 2}\cell\row
\intbl{\b S3}\cell{Input 3}\cell\row
\intbl{\b S4}\cell{Input 4}\cell\row
\intbl{\b S5}\cell{Gain multiplier (real) for input 1}\cell\row
\intbl{\b S6}\cell{Gain multiplier (real) for input 2}\cell\row
\intbl{\b S7}\cell{Gain multiplier (real) for input 3}\cell\row
\intbl{\b S8}\cell{Gain multiplier (real) for input 4}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output equals S5<S1> + S6<S2> + S7<S3> + S8<S4>}\cell\row\par
#66
\intbl{\b S1}\cell{Analog input}\cell\row
\intbl{\b S2}\cell{Mode (0=sample 1=mean 2=minimum 3=maximum 4=sum)}\cell\row
\intbl{\b S3}\cell{Trend resolution (0=standard 1=enhanced)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is last value saved}\cell\row\par
#67
#68
\intbl{\b S1}\cell{Engineering units ID}\cell\row
\intbl{\b S2}\cell{High limit}\cell\row
\intbl{\b S3}\cell{Low limit}\cell\row
\intbl{\b S4}\cell{Initial output value}\cell\row
\intbl{\b S5}\cell{Track flag}\cell\row
\intbl{\b S6}\cell{Track value}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is value of S6 when S5 is 1, else output equals S4}\cell\row\par
#69
\intbl{\b S1}\cell{Input}\cell\row
\intbl{\b S2}\cell{Alarm condition tested (0=absolute 1=deviation 2=device drivers)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output indicates high alarm: 0 - no alarm, 1 - alarm}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Output indicates low alarm: 0 - no alarm, 1 - alarm}\cell\row\par
#70
\intbl{\b S1}\cell{Input type}\cell\row
\intbl{\b S2}\cell{Engineering units type}\cell\row
\intbl{\b S3}\cell{Engineering units ID}\cell\row
\intbl{\b S4}\cell{Engineering units zero of input}\cell\row
\intbl{\b S5}\cell{Engineering units span of input}\cell\row
\intbl{\b S6}\cell{Significant change (percent of span)}\cell\row
\intbl{\b S7}\cell{High alarm point limit value}\cell\row
\intbl{\b S8}\cell{Low alarm point limit value}\cell\row
\intbl{\b S9}\cell{Leadwire resistance in ohms}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is value of analog input}\cell\row\par
#71
\intbl{\b S1}\cell{Configuration lock/1=lock 0=unlock}\cell\row
\intbl{\b S2}\cell{Alarm deadband high/low reports (percent span)}\cell\row
\intbl{\b S3}\cell{Cable length from master to termination device (feet)}\cell\row
\intbl{\b S4}\cell{Slave 0 blocks 1-8 minimum time}\cell\row
\intbl{\b S5}\cell{Slave 0 blocks 1-8 maximum time}\cell\row
\intbl{\b S6}\cell{Slave 1 blocks 9-16 minimum time}\cell\row
\intbl{\b S7}\cell{Slave 1 blocks 9-16 maximum time}\cell\row
\intbl{\b S8}\cell{Slave 2 blocks 17-24 minimum time}\cell\row
\intbl{\b S9}\cell{Slave 2 blocks 17-24 maximum time}\cell\row
\intbl{\b S10}\cell{Slave 3 blocks 25-32 minimum time}\cell\row
\intbl{\b S11}\cell{Slave 3 blocks 25-32 maximum time}\cell\row
\intbl{\b S12}\cell{Slave 4 blocks 33-40 minimum time}\cell\row
\intbl{\b S13}\cell{Slave 4 blocks 33-40 maximum time}\cell\row
\intbl{\b S14}\cell{Slave 5 blocks 41-48 minimum time}\cell\row
\intbl{\b S15}\cell{Slave 5 blocks 41-48 maximum time}\cell\row
\intbl{\b S16}\cell{Slave 6 blocks 49-56 minimum time}\cell\row
\intbl{\b S17}\cell{Slave 6 blocks 49-56 maximum time}\cell\row
\intbl{\b S18}\cell{Slave 7 blocks 57-64 minimum time}\cell\row
\intbl{\b S19}\cell{Slave 7 blocks 57-64 maximum time}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 75}\cell{None}\cell{No output}\cell\row\par
#72
\intbl{\b S1}\cell{Slave type 0 For all slaves}\cell\row
\intbl{\b S2}\cell{Slave type 1 the values mean:}\cell\row
\intbl{\b S3}\cell{Slave type 2 - 0 - undefined}\cell\row
\intbl{\b S4}\cell{Slave type 3 - 1 - thermocouple}\cell\row
\intbl{\b S5}\cell{Slave type 4 - 2 - RTD}\cell\row
\intbl{\b S6}\cell{Slave type 5 - 3 - high level}\cell\row
\intbl{\b S7}\cell{Slave type 6}\cell\row
\intbl{\b S8}\cell{Slave type 7}\cell\row
\intbl{\b S9}\cell{Slave number for thermocouple group A cold junction}\cell\row
\intbl{\b S10}\cell{Slave number for thermocouple group A RTD}\cell\row
\intbl{\b S11}\cell{Slave number for thermocouple group B cold junction}\cell\row
\intbl{\b S12}\cell{Slave number for thermocouple group B RTD}\cell\row
\intbl{\b S13}\cell{Slave number for thermocouple group C cold junction}\cell\row
\intbl{\b S14}\cell{Slave number for thermocouple group C RTD}\cell\row
\intbl{\b S15}\cell{Slave number for thermocouple group D cold junction}\cell\row
\intbl{\b S16}\cell{Slave number for thermocouple group D RTD}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 76}\cell{None}\cell{No output}\cell\row\par
#73
\intbl{\b S1}\cell{Offset}\cell\row
\intbl{\b S2}\cell{Gain}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is raw value of input in mv}\cell\row\par
#74
\intbl{\b S1}\cell{Command (1-12)}\cell\row
\intbl{\b S2}\cell{Number of points to be calibrated}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 80}\cell{Real}\cell{No output}\cell\row\par
#75
\intbl{\b S1}\cell{Operation status}\cell\row
\intbl{\b S2}\cell{Status of slave of point number 1}\cell\row
\intbl{\b S3}\cell{Status of slave of point number 2}\cell\row
\intbl{\b S4}\cell{Status of slave of point number 3}\cell\row
\intbl{\b S5}\cell{Status of slave of point number 4}\cell\row
\intbl{\b S6}\cell{Status of slave of point number 5}\cell\row
\intbl{\b S7}\cell{Status of slave of point number 6}\cell\row
\intbl{\b S8}\cell{Status of slave of point number 7}\cell\row
\intbl{\b S9}\cell{Status of slave of point number 8}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 81}\cell{Real}\cell{No output}\cell\row\par
#76
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 90}\cell{Real}\cell{Output is RTD pair A thermocouple termination device temperature}\cell\row
\intbl{\b 91}\cell{Real}\cell{Output is RTD pair B thermocouple termination device temperature}\cell\row
\intbl{\b 92}\cell{Real}\cell{Output is RTD pair C thermocouple termination device temperature}\cell\row
\intbl{\b 93}\cell{Real}\cell{Output is RTD pair D thermocouple termination device temperature}\cell\row
\intbl{\b 94}\cell{Real}\cell{Output is system trend time, hours}\cell\row
\intbl{\b 95}\cell{Real}\cell{Output is system trend time, minutes}\cell\row
\intbl{\b 96}\cell{Real}\cell{Output is system trend time, seconds}\cell\row
\intbl{\b 97}\cell{Real}\cell{Output is module revision level}\cell\row\par
#77
\intbl{\b S1}\cell{Point services status for slave number 0}\cell\row
\intbl{\b S2}\cell{Point services status for slave number 1}\cell\row
\intbl{\b S3}\cell{Point services status for slave number 2}\cell\row
\intbl{\b S4}\cell{Point services status for slave number 3}\cell\row
\intbl{\b S5}\cell{Point services status for slave number 4}\cell\row
\intbl{\b S6}\cell{Point services status for slave number 5}\cell\row
\intbl{\b S7}\cell{Point services status for slave number 6}\cell\row
\intbl{\b S8}\cell{Point services status for slave number 7}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 89}\cell{Real}\cell{No output}\cell\row\par
#78
\intbl{\b S1}\cell{Trend definition block number 1}\cell\row
\intbl{\b S2}\cell{Trend definition block number 2}\cell\row
\intbl{\b S3}\cell{Trend definition block number 3}\cell\row
\intbl{\b S4}\cell{Trend definition block number 4}\cell\row
\intbl{\b S5}\cell{Trend definition block number 5}\cell\row
\intbl{\b S6}\cell{Trend definition block number 6}\cell\row
\intbl{\b S7}\cell{Trend definition block number 7}\cell\row
\intbl{\b S8}\cell{Trend definition block number 8}\cell\row
\intbl{\b S9}\cell{Trend definition block number 9}\cell\row
\intbl{\b S10}\cell{Trend definition block number 10}\cell\row
\intbl{\b S11}\cell{Trend definition block number 11}\cell\row
\intbl{\b S12}\cell{Trend definition block number 12}\cell\row
\intbl{\b S13}\cell{Trend definition block number 13}\cell\row
\intbl{\b S14}\cell{Trend definition block number 14}\cell\row
\intbl{\b S15}\cell{Trend definition block number 15}\cell\row
\intbl{\b S16}\cell{Trend definition block number 16}\cell\row
\intbl{\b S17}\cell{Trend definition block number 17}\cell\row
\intbl{\b S18}\cell{Trend definition block number 18}\cell\row
\intbl{\b S19}\cell{Trend definition block number 19}\cell\row
\intbl{\b S20}\cell{Trend definition block number 20}\cell\row
\intbl{\b S21}\cell{Trend definition block number 21}\cell\row
\intbl{\b S22}\cell{Trend definition block number 22}\cell\row
\intbl{\b S23}\cell{Trend definition block number 23}\cell\row
\intbl{\b S24}\cell{Trend definition block number 24}\cell\row
\intbl{\b S25}\cell{Trend definition block number 25}\cell\row
\intbl{\b S26}\cell{Trend definition block number 26}\cell\row
\intbl{\b S27}\cell{Trend definition block number 27}\cell\row
\intbl{\b S28}\cell{Trend definition block number 28}\cell\row
\intbl{\b S29}\cell{Trend definition block number 29}\cell\row
\intbl{\b S30}\cell{Trend definition block number 30}\cell\row
\intbl{\b S31}\cell{Trend definition block number 31}\cell\row
\intbl{\b S32}\cell{Trend definition block number 32}\cell\row
\intbl{\b S33}\cell{Trend definition block number 33}\cell\row
\intbl{\b S34}\cell{Trend definition block number 34}\cell\row
\intbl{\b S35}\cell{Trend definition block number 35}\cell\row
\intbl{\b S36}\cell{Trend definition block number 36}\cell\row
\intbl{\b S37}\cell{Trend definition block number 37}\cell\row
\intbl{\b S38}\cell{Trend definition block number 38}\cell\row
\intbl{\b S39}\cell{Trend definition block number 39}\cell\row
\intbl{\b S40}\cell{Trend definition block number 40}\cell\row
\intbl{\b S41}\cell{Trend definition block number 41}\cell\row
\intbl{\b S42}\cell{Trend definition block number 42}\cell\row
\intbl{\b S43}\cell{Trend definition block number 43}\cell\row
\intbl{\b S44}\cell{Trend definition block number 44}\cell\row
\intbl{\b S45}\cell{Trend definition block number 45}\cell\row
\intbl{\b S46}\cell{Trend definition block number 46}\cell\row
\intbl{\b S47}\cell{Trend definition block number 47}\cell\row
\intbl{\b S48}\cell{Trend definition block number 48}\cell\row
\intbl{\b S49}\cell{Trend definition block number 49}\cell\row
\intbl{\b S50}\cell{Trend definition block number 50}\cell\row
\intbl{\b S51}\cell{Trend definition block number 51}\cell\row
\intbl{\b S52}\cell{Trend definition block number 52}\cell\row
\intbl{\b S53}\cell{Trend definition block number 53}\cell\row
\intbl{\b S54}\cell{Trend definition block number 54}\cell\row
\intbl{\b S55}\cell{Trend definition block number 55}\cell\row
\intbl{\b S56}\cell{Trend definition block number 56}\cell\row
\intbl{\b S57}\cell{Trend definition block number 57}\cell\row
\intbl{\b S58}\cell{Trend definition block number 58}\cell\row
\intbl{\b S59}\cell{Trend definition block number 59}\cell\row
\intbl{\b S60}\cell{Trend definition block number 60}\cell\row
\intbl{\b S61}\cell{Trend definition block number 61}\cell\row
\intbl{\b S62}\cell{Trend definition block number 62}\cell\row
\intbl{\b S63}\cell{Trend definition block number 63}\cell\row
\intbl{\b S64}\cell{Trend definition block number 64}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 77}\cell{Real}\cell{No output}\cell\row\par
#79
\intbl{\b S1}\cell{CIS slave address}\cell\row
\intbl{\b S2}\cell{Zero of analog input 1}\cell\row
\intbl{\b S3}\cell{Span of analog input 1}\cell\row
\intbl{\b S4}\cell{Zero of analog input 2}\cell\row
\intbl{\b S5}\cell{Span of analog input 2}\cell\row
\intbl{\b S6}\cell{Zero of analog input 3}\cell\row
\intbl{\b S7}\cell{Span of analog input 3}\cell\row
\intbl{\b S8}\cell{Zero of analog input 4}\cell\row
\intbl{\b S9}\cell{Span of analog input 4}\cell\row
\intbl{\b S10}\cell{Input block address/analog output 1}\cell\row
\intbl{\b S11}\cell{Input block address/analog output 2}\cell\row
\intbl{\b S12}\cell{Digital input #1 sense (0 = closed)}\cell\row
\intbl{\b S13}\cell{Digital input #2 sense (1 = closed)}\cell\row
\intbl{\b S14}\cell{Digital input #3 sense (2 = unused)}\cell\row
\intbl{\b S15}\cell{Input block address/digital output 1}\cell\row
\intbl{\b S16}\cell{Input block address/digital output 2}\cell\row
\intbl{\b S17}\cell{Input block address/digital output 3}\cell\row
\intbl{\b S18}\cell{Input block address/digital output 4}\cell\row
\intbl{\b S19}\cell{Failure action (0=trip 1=continue)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is analog input 1}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is analog input 2}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is analog input 3}\cell\row
\intbl{\b N+3}\cell{Real}\cell{Output is analog input 4}\cell\row
\intbl{\b N+4}\cell{Real}\cell{Output is analog output 1 feedback}\cell\row
\intbl{\b N+5}\cell{Real}\cell{Output is analog output 2 feedback}\cell\row
\intbl{\b N+6}\cell{Bit}\cell{Output is digital input 1}\cell\row
\intbl{\b N+7}\cell{Bit}\cell{Output is digital input 2}\cell\row
\intbl{\b N+8}\cell{Bit}\cell{Output is digital input 3}\cell\row
\intbl{\b N+9}\cell{Bit}\cell{Output indicates slave status: 0 - good, 1 - bad}\cell\row\par
#80
\intbl{\b S1}\cell{Process value}\cell\row
\intbl{\b S2}\cell{Setpoint track signal}\cell\row
\intbl{\b S3}\cell{Auto signal}\cell\row
\intbl{\b S4}\cell{Control output track signal}\cell\row
\intbl{\b S5}\cell{Track switch (TS) 1=track 0=norm}\cell\row
\intbl{\b S6}\cell{Initial mode of station after startup}\cell\row
\intbl{\b S7}\cell{Process value high alarm limit in engineering units}\cell\row
\intbl{\b S8}\cell{Process value low alarm limit in engineering units}\cell\row
\intbl{\b S9}\cell{Process value minus setpoint deviation alarm limit}\cell\row
\intbl{\b S10}\cell{Process value signal span in engineering units}\cell\row
\intbl{\b S11}\cell{Process value zero value in engineering units}\cell\row
\intbl{\b S12}\cell{Process value engineering units ID (OIU use only)}\cell\row
\intbl{\b S13}\cell{Setpoint signal span in engineering units}\cell\row
\intbl{\b S14}\cell{Setpoint zero value in engineering units}\cell\row
\intbl{\b S15}\cell{Setpoint engineering units ID (OIU use only)}\cell\row
\intbl{\b S16}\cell{SAC/DCS station address (255=no station)}\cell\row
\intbl{\b S17}\cell{Computer failure mode}\cell\row
\intbl{\b S18}\cell{Transfer to manual signal}\cell\row
\intbl{\b S19}\cell{Transfer to auto signal}\cell\row
\intbl{\b S20}\cell{Transfer cascade/ratio signal}\cell\row
\intbl{\b S21}\cell{Transfer to local signal}\cell\row
\intbl{\b S22}\cell{Transfer to computer signal}\cell\row
\intbl{\b S23}\cell{Station type (0-2=basic 3=ratio 4=cascade)}\cell\row
\intbl{\b S24}\cell{High absolute alarm flag}\cell\row
\intbl{\b S25}\cell{Low absolute alarm flag}\cell\row
\intbl{\b S26}\cell{High deviation alarm flag}\cell\row
\intbl{\b S27}\cell{Low deviation alarm flag}\cell\row
\intbl{\b S28}\cell{Analog output}\cell\row
\intbl{\b S29}\cell{Switch for setpoint to track S2}\cell\row
\intbl{\b S30}\cell{Switch for setpoint to track S1}\cell\row
\intbl{\b S31}\cell{Computer watchdog time period (seconds)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Control output}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is setpoint}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Automatic mode: 0 - manual, 1 - automatic}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Control state: 0 - local, 1 - computer}\cell\row
\intbl{\b N+4}\cell{Bit}\cell{Cascade/ratio mode: 0 - BASIC, 1 - cascade/ratio}\cell\row
\intbl{\b N+5}\cell{Bit}\cell{Computer status: 0 - okay, 1 - failed}\cell\row\par
#81
\intbl{\b S1}\cell{LED mode (0-normal MFP/MFC status 1-show memory)}\cell\row
\intbl{\b S2}\cell{Memory display address/most significant byte}\cell\row
\intbl{\b S3}\cell{Memory display address/middle byte}\cell\row
\intbl{\b S4}\cell{Memory display address/least significant byte}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 0}\cell{Bit}\cell{Output is constant 0}\cell\row
\intbl{\b 1}\cell{Bit}\cell{Output is constant 1}\cell\row
\intbl{\b 2}\cell{Bit}\cell{Output is constant 0}\cell\row
\intbl{\b 3}\cell{Real}\cell{Output is constant -100.000}\cell\row
\intbl{\b 4}\cell{Real}\cell{Output is constant -1.000}\cell\row
\intbl{\b 5}\cell{Real}\cell{Output is constant 0.000}\cell\row
\intbl{\b 6}\cell{Real}\cell{Output is constant 1.000}\cell\row
\intbl{\b 7}\cell{Real}\cell{Output is constant 100.000}\cell\row
\intbl{\b 8}\cell{Real}\cell{Output is constant -9.2 E 18}\cell\row
\intbl{\b 9}\cell{Real}\cell{Output is constant 9.2 E 18}\cell\row
\intbl{\b 10}\cell{Bit}\cell{Start up in progress: 0 - no, 1 - yes}\cell\row
\intbl{\b 11}\cell{Real}\cell{Output is selected memory display value}\cell\row
\intbl{\b 12}\cell{Real}\cell{Output is system free time in percent}\cell\row
\intbl{\b 13}\cell{Real}\cell{Output is revision level}\cell\row
\intbl{\b 14}\cell{Real}\cell{Reserved}\cell\row\par
#82
\intbl{\b S1}\cell{Tune/modify lock and time units (X1=sec X2=min)}\cell\row
\intbl{\b S2}\cell{Target period}\cell\row
\intbl{\b S3}\cell{Segment priority (0=lowest)}\cell\row
\intbl{\b S4}\cell{Checkpoint period}\cell\row
\intbl{\b S5}\cell{PID external reset (0=normal 1=reset)}\cell\row
\intbl{\b S6}\cell{Maximum derivative gain for PID}\cell\row
\intbl{\b S7}\cell{Minimum exception report time}\cell\row
\intbl{\b S8}\cell{Maximum exception report time}\cell\row
\intbl{\b S9}\cell{Significant change (percent span)}\cell\row
\intbl{\b S10}\cell{Alarm deadband for high and low alarm reports}\cell\row
\intbl{\b S11}\cell{Alarm deadband for deviation reports}\cell\row
\intbl{\b S12}\cell{Reserved}\cell\row
\intbl{\b S13}\cell{Module bus update time}\cell\row
\intbl{\b S14}\cell{Cycle time alarm limit (seconds)}\cell\row
\intbl{\b S15}\cell{Auto sequencing (0=off 1=on)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is elapsed time of previous cycle}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is elapsed time of current cycle}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is processor utilization}\cell\row
\intbl{\b N+3}\cell{Real}\cell{Output is checkpoint overrun count}\cell\row
\intbl{\b N+4}\cell{Real}\cell{Output is cycle time overrun time}\cell\row\par
#83
\intbl{\b S1}\cell{Expander bus slave address}\cell\row
\intbl{\b S2}\cell{Slave definition = hold + type + group}\cell\row
\intbl{\b S3}\cell{Slave failure action (0=trip 1=continue)}\cell\row
\intbl{\b S4}\cell{Output 1}\cell\row
\intbl{\b S5}\cell{Output 2}\cell\row
\intbl{\b S6}\cell{Output 3}\cell\row
\intbl{\b S7}\cell{Output 4}\cell\row
\intbl{\b S8}\cell{Output 5}\cell\row
\intbl{\b S9}\cell{Output 6}\cell\row
\intbl{\b S10}\cell{Output 7}\cell\row
\intbl{\b S11}\cell{Output 8}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Status of group: 0 - good, 1 - bad (slave failed to respond)}\cell\row\par
#84
\intbl{\b S1}\cell{Slave address}\cell\row
\intbl{\b S2}\cell{Input group (0=0-7 1=8-15)}\cell\row
\intbl{\b S3}\cell{Slave failure action (0=trip 1=continue)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output 1 with quality}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Output 2 with quality}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Output 3 with quality}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Output 4 with quality}\cell\row
\intbl{\b N+4}\cell{Bit}\cell{Output 5 with quality}\cell\row
\intbl{\b N+5}\cell{Bit}\cell{Output 6 with quality}\cell\row
\intbl{\b N+6}\cell{Bit}\cell{Output 7 with quality}\cell\row
\intbl{\b N+7}\cell{Bit}\cell{Output 8 with quality}\cell\row\par
#85
\intbl{\b S1}\cell{Up trigger}\cell\row
\intbl{\b S2}\cell{Down trigger}\cell\row
\intbl{\b S3}\cell{Reset/run}\cell\row
\intbl{\b S4}\cell{Release/hold}\cell\row
\intbl{\b S5}\cell{Counter startup/reset value}\cell\row
\intbl{\b S6}\cell{High alarm value}\cell\row
\intbl{\b S7}\cell{Low alarm value}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is value of counter}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{High alarm: 0 - no alarm, 1 - count has reached high limit}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Low alarm: 0 - no alarm, 1 - count has reached low limit}\cell\row\par
#86
\intbl{\b S1}\cell{Reset/run}\cell\row
\intbl{\b S2}\cell{Release/hold}\cell\row
\intbl{\b S3}\cell{Time units (0=seconds 1=minutes 2=hours 3=days)}\cell\row
\intbl{\b S4}\cell{Timer alarm value}\cell\row
\intbl{\b S5}\cell{Timer startup/reset value}\cell\row
\intbl{\b S6}\cell{Up/down indicator (0=up 1=down)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is value of timer}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Time alarm: 0 - alarm time not reached, 1 - alarm time reached}\cell\row\par
#87
\intbl{\b S1}\cell{Slave address}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Slave status: 0 - good, 1 - bad (slave failed to respond)}\cell\row\par
#88
\intbl{\b S1}\cell{Logic station address}\cell\row
\intbl{\b S2}\cell{Logic station interface}\cell\row
\intbl{\b S3}\cell{Group A block address output number 1}\cell\row
\intbl{\b S4}\cell{Group A block address output number 2}\cell\row
\intbl{\b S5}\cell{Group A block address output number 3}\cell\row
\intbl{\b S6}\cell{Group A block address output number 4}\cell\row
\intbl{\b S7}\cell{Group A block address output number 5}\cell\row
\intbl{\b S8}\cell{Group A block address output number 6}\cell\row
\intbl{\b S9}\cell{Group A block address output number 7}\cell\row
\intbl{\b S10}\cell{Group A block address output number 8}\cell\row
\intbl{\b S11}\cell{Group B block address output number 1}\cell\row
\intbl{\b S12}\cell{Group B block address output number 2}\cell\row
\intbl{\b S13}\cell{Group B block address output number 3}\cell\row
\intbl{\b S14}\cell{Group B block address output number 4}\cell\row
\intbl{\b S15}\cell{Group B block address output number 5}\cell\row
\intbl{\b S16}\cell{Group B block address output number 6}\cell\row
\intbl{\b S17}\cell{Group B block address output number 7}\cell\row
\intbl{\b S18}\cell{Group B block address output number 8}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is value of push button 1: 0 - open, 1 - closed}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Output is value of push button 2: 0 - open, 1 - closed}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Output is value of push button 3: 0 - open, 1 - closed}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Output is value of push button 4: 0 - open, 1 - closed}\cell\row
\intbl{\b N+4}\cell{Bit}\cell{Output is value of push button 5: 0 - open, 1 - closed}\cell\row
\intbl{\b N+5}\cell{Bit}\cell{Output is value of push button 6: 0 - open, 1 - closed}\cell\row
\intbl{\b N+6}\cell{Bit}\cell{Output is value of push button 7: 0 - open, 1 - closed}\cell\row
\intbl{\b N+7}\cell{Bit}\cell{Output is value of push button 8: 0 - open, 1 - closed}\cell\row
\intbl{\b N+8}\cell{Bit}\cell{Output indicates DLS status: 0 - good, 1 - bad}\cell\row\par
#89
\intbl{\b S1}\cell{Dummy specification not used}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is network type}\cell\row\par
#90
\intbl{\b S1}\cell{Configuration lock/1=lock 0=unlock}\cell\row
\intbl{\b S2}\cell{Base module bus I/O period (sec)}\cell\row
\intbl{\b S3}\cell{SAC/DCS communication rate + halt/error on slave trip + redundancy}\cell\row
\intbl{\b S4}\cell{Module startup time (seconds)}\cell\row
\intbl{\b S5}\cell{Logic station poll rate (seconds)}\cell\row
\intbl{\b S6}\cell{SOE monitor time synchronization flag}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 20}\cell{Real}\cell{Output is current hour}\cell\row
\intbl{\b 21}\cell{Real}\cell{Output is current minute}\cell\row
\intbl{\b 22}\cell{Real}\cell{Output is current second}\cell\row
\intbl{\b 23}\cell{Bit}\cell{Time/date synchronization: 0 - time/date invalid, 1 - time/date valid}\cell\row
\intbl{\b 24}\cell{Real}\cell{Output is current year (0 - 99)}\cell\row
\intbl{\b 25}\cell{Real}\cell{Output is current month (1 - 12)}\cell\row
\intbl{\b 26}\cell{Real}\cell{Output is current day (1 - 31)}\cell\row
\intbl{\b 27}\cell{Real}\cell{Output is current day of week (1 - 7, Sunday = 1)}\cell\row
\intbl{\b 28}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 29}\cell{Real}\cell{Reserved}\cell\row\par
#91
\intbl{\b S1}\cell{Action on error (0=trip MFC 1=suspend)}\cell\row
\intbl{\b S2}\cell{Load/run flag (0=auto 1=manual)}\cell\row
\intbl{\b S3}\cell{String space allocation (NVRAM - 1K byte increments)}\cell\row
\intbl{\b S4}\cell{Data space allocation (RAM - 1K byte increments)}\cell\row
\intbl{\b S5}\cell{Program space allocation (NVRAM - 1K byte increments)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is value set by BOUT command in BASIC program}\cell\row\par
#92
\intbl{\b S1}\cell{Value that BASIC can read (SYSVAR)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is value set by BOUT command in BASIC program}\cell\row\par
#93
\intbl{\b S1}\cell{Dummy specification not used}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is value set by BOUT command in BASIC program}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is value set by BOUT command in BASIC program}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is value set by BOUT command in BASIC program}\cell\row
\intbl{\b N+3}\cell{Real}\cell{Output is value set by BOUT command in BASIC program}\cell\row\par
#94
\intbl{\b S1}\cell{Dummy specification not used}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is value set by BOUT command in BASIC program}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Output is value set by BOUT command in BASIC program}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Output is value set by BOUT command in BASIC program}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Output is value set by BOUT command in BASIC program}\cell\row\par
#95
\intbl{\b S1}\cell{Module bus update time (seconds)}\cell\row
\intbl{\b S2}\cell{Target module address}\cell\row
\intbl{\b S3}\cell{Module status byte number}\cell\row
\intbl{\b S4}\cell{Offline detection flag (0=off 1=on)}\cell\row
\intbl{\b S5}\cell{Bit 0 of byte selected to be monitored (0=no 1=yes)}\cell\row
\intbl{\b S6}\cell{Bit 1 of byte selected to be monitored (0=no 1=yes)}\cell\row
\intbl{\b S7}\cell{Bit 2 of byte selected to be monitored (0=no 1=yes)}\cell\row
\intbl{\b S8}\cell{Bit 3 of byte selected to be monitored (0=no 1=yes)}\cell\row
\intbl{\b S9}\cell{Bit 4 of byte selected to be monitored (0=no 1=yes)}\cell\row
\intbl{\b S10}\cell{Bit 5 of byte selected to be monitored (0=no 1=yes)}\cell\row
\intbl{\b S11}\cell{Bit 6 of byte selected to be monitored (0=no 1=yes)}\cell\row
\intbl{\b S12}\cell{Bit 7 of byte selected to be monitored (0=no 1=yes)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is masked status/quality: 0 - good, 1 - bad}\cell\row\par
#96
\intbl{\b S1}\cell{Input 1}\cell\row
\intbl{\b S2}\cell{Input 2}\cell\row
\intbl{\b S3}\cell{Select input flag (0=S1 1=S2)}\cell\row
\intbl{\b S4}\cell{Deviation limit}\cell\row
\intbl{\b S5}\cell{Rate of change limit}\cell\row
\intbl{\b S6}\cell{Deadband on rate of change}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is value of selected analog input}\cell\row\par
#97
\intbl{\b S1}\cell{Input 1}\cell\row
\intbl{\b S2}\cell{Input 2}\cell\row
\intbl{\b S3}\cell{Select input flag (0=S1 1=S2)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is value of selected digital input}\cell\row\par
#98
\intbl{\b S1}\cell{Boolean status slave 1}\cell\row
\intbl{\b S2}\cell{Boolean status slave 1}\cell\row
\intbl{\b S3}\cell{I/O quality slave 1}\cell\row
\intbl{\b S4}\cell{I/O quality slave 1}\cell\row
\intbl{\b S5}\cell{Boolean status slave 2}\cell\row
\intbl{\b S6}\cell{Boolean status slave 2}\cell\row
\intbl{\b S7}\cell{I/O quality slave 2}\cell\row
\intbl{\b S8}\cell{I/O quality slave 2}\cell\row
\intbl{\b S9}\cell{Toggle input}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Selected slave: 0 - slave 1, 1 - slave 2}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Interlock status: 0 - one or both slaves good, 1 - both slaves bad}\cell\row\par
#99
\intbl{\b S1}\cell{Log type (0=standard 1=summary 2= pre-fault 3=post-fault 4=snapshot)}\cell\row
\intbl{\b S2}\cell{Maximum number of events logged}\cell\row
\intbl{\b S3}\cell{Maximum age of events (sec)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Events logged: 0 - no, 1 - yes}\cell\row\par
#100
\intbl{\b S1}\cell{Block address DO output value 1}\cell\row
\intbl{\b S2}\cell{Block address DI readback value 1}\cell\row
\intbl{\b S3}\cell{Block address DO output value 2}\cell\row
\intbl{\b S4}\cell{Block address DI readback value 2}\cell\row
\intbl{\b S5}\cell{Block address DO output value 3}\cell\row
\intbl{\b S6}\cell{Block address DI readback value 3}\cell\row
\intbl{\b S7}\cell{Block address DO output value 4}\cell\row
\intbl{\b S8}\cell{Block address DI readback value 4}\cell\row
\intbl{\b S9}\cell{Block address DO output value 5}\cell\row
\intbl{\b S10}\cell{Block address DI readback value 5}\cell\row
\intbl{\b S11}\cell{Block address DO output value 6}\cell\row
\intbl{\b S12}\cell{Block address DI readback value 6}\cell\row
\intbl{\b S13}\cell{Block address DO output value 7}\cell\row
\intbl{\b S14}\cell{Block address DI readback value 7}\cell\row
\intbl{\b S15}\cell{Block address DO output value 8}\cell\row
\intbl{\b S16}\cell{Block address DI readback value 8}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Error status: 0 - all digital outputs match digital inputs, 1 - one or more digital outputs do not match digital inputs}\cell\row\par
#101
\intbl{\b S1}\cell{Input 1}\cell\row
\intbl{\b S2}\cell{Input 2}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is logical XOR of inputs}\cell\row\par
#102
\intbl{\b S1}\cell{Expander bus slave address}\cell\row
\intbl{\b S2}\cell{Selected channel (1-8)}\cell\row
\intbl{\b S3}\cell{Pulse trigger level (0=low-high 1=high-low)}\cell\row
\intbl{\b S4}\cell{Expected period range}\cell\row
\intbl{\b S5}\cell{Gain}\cell\row
\intbl{\b S6}\cell{High alarm value}\cell\row
\intbl{\b S7}\cell{Low alarm value}\cell\row
\intbl{\b S8}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is period times gain}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Period high alarm: 0 - no alarm, 1 - high alarm}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Period low alarm: 0 - no alarm, 1 - low alarm}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Slave communication status: 0 - good, 1 - no response, illegal response or no input pulse received}\cell\row\par
#103
\intbl{\b S1}\cell{Expander bus slave address}\cell\row
\intbl{\b S2}\cell{Selected channel (1-8)}\cell\row
\intbl{\b S3}\cell{Pulse trigger level (0=low-high 1=high-low)}\cell\row
\intbl{\b S4}\cell{Expected period range}\cell\row
\intbl{\b S5}\cell{Gain}\cell\row
\intbl{\b S6}\cell{High alarm value}\cell\row
\intbl{\b S7}\cell{Low alarm value}\cell\row
\intbl{\b S8}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is frequency times gain}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Frequency high alarm: 0 - no alarm, 1 - high alarm}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Frequency low alarm: 0 - no alarm, 1 - low alarm}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Slave communication status: 0 - good, 1 - no response, illegal response or frequency out of range}\cell\row\par
#104
\intbl{\b S1}\cell{Expander bus slave address}\cell\row
\intbl{\b S2}\cell{Selected channel (1-8)}\cell\row
\intbl{\b S3}\cell{Pulse trigger level (0=low-high 1=high-low)}\cell\row
\intbl{\b S4}\cell{Initial value}\cell\row
\intbl{\b S5}\cell{Totalization direction (0=positive 1=negative)}\cell\row
\intbl{\b S6}\cell{Reset flag (0=continue totalization 1=reset)}\cell\row
\intbl{\b S7}\cell{Hold flag (0=continue totalization 1=hold accumulated total)}\cell\row
\intbl{\b S8}\cell{Auto reset on alarm limit flag}\cell\row
\intbl{\b S9}\cell{Gain}\cell\row
\intbl{\b S10}\cell{Alarm limit}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is totalized value times gain}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Totalized value alarm: 0 - no alarm, 1 - alarm}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Slave communication status: 0 - good, 1 - no response, illegal response or no input pulse received}\cell\row\par
#105
\intbl{\b S1}\cell{Configuration lock/1=lock 0=unlock}\cell\row
\intbl{\b S2}\cell{Maximum number of digital exception reports allowed}\cell\row
\intbl{\b S3}\cell{Time delay (in sec) on start up}\cell\row
\intbl{\b S4}\cell{Maximum configurable block number}\cell\row
\intbl{\b S5}\cell{Spare}\cell\row
\intbl{\b S6}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 0}\cell{Bit}\cell{Output is constant 0}\cell\row
\intbl{\b 1}\cell{Bit}\cell{Output is constant 1}\cell\row
\intbl{\b 2}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 3}\cell{Real}\cell{Output is constant -100.0}\cell\row
\intbl{\b 4}\cell{Real}\cell{Output is constant -1.0}\cell\row
\intbl{\b 5}\cell{Real}\cell{Output is constant 0.0}\cell\row
\intbl{\b 6}\cell{Real}\cell{Output is constant 1.0}\cell\row
\intbl{\b 7}\cell{Real}\cell{Output is constant 100.0}\cell\row
\intbl{\b 8}\cell{Real}\cell{Output is constant -9.2E18}\cell\row
\intbl{\b 9}\cell{Real}\cell{Output is constant 9.2E18}\cell\row
\intbl{\b 10}\cell{Bit}\cell{Startup complete: 0 - no, 1 - yes}\cell\row
\intbl{\b 11}\cell{-}\cell{Reserved}\cell\row
\intbl{\b 12}\cell{Real}\cell{Output is CPU free time in percent}\cell\row
\intbl{\b 13}\cell{Real}\cell{Output is revision level}\cell\row
\intbl{\b 14}\cell{-}\cell{Reserved}\cell\row\par
#106
\intbl{\b S1}\cell{Segment priority (0=lowest)}\cell\row
\intbl{\b S2}\cell{Auto sequencing (0=off 1=on)}\cell\row
\intbl{\b S3}\cell{Period (seconds)}\cell\row
\intbl{\b S4}\cell{Cycle time alarm limit (seconds)}\cell\row
\intbl{\b S5}\cell{Minimum exception report time}\cell\row
\intbl{\b S6}\cell{Maximum exception report time}\cell\row
\intbl{\b S7}\cell{Alarm deadband high/low reports (percent span)}\cell\row
\intbl{\b S8}\cell{Module bus update time (seconds)}\cell\row
\intbl{\b S9}\cell{Spare}\cell\row
\intbl{\b S10}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is elapsed time of previous cycle}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is elapsed time of current cycle}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is segment processor utilization in percent}\cell\row\par
#107
\intbl{\b S1}\cell{Slave address}\cell\row
\intbl{\b S2}\cell{Slave address for logic station}\cell\row
\intbl{\b S3}\cell{Additional block count for group address}\cell\row
\intbl{\b S4}\cell{Spare}\cell\row
\intbl{\b S5}\cell{Definition of group 0}\cell\row
\intbl{\b S6}\cell{Definition of group 1}\cell\row
\intbl{\b S7}\cell{Definition of group 2}\cell\row
\intbl{\b S8}\cell{Definition of group 3}\cell\row
\intbl{\b S9}\cell{Definition of group 4}\cell\row
\intbl{\b S10}\cell{Definition of group 5}\cell\row
\intbl{\b S11}\cell{Definition of group 6}\cell\row
\intbl{\b S12}\cell{Definition of group 7}\cell\row
\intbl{\b S13}\cell{Definition of group 8}\cell\row
\intbl{\b S14}\cell{Definition of group 9}\cell\row
\intbl{\b S15}\cell{Definition of group 10}\cell\row
\intbl{\b S16}\cell{Definition of group 11}\cell\row
\intbl{\b S17}\cell{Definition of group 12}\cell\row
\intbl{\b S18}\cell{Definition of group 13}\cell\row
\intbl{\b S19}\cell{Definition of group 14}\cell\row
\intbl{\b S20}\cell{Definition of group 15}\cell\row
\intbl{\b S21}\cell{Definition of group 16}\cell\row
\intbl{\b S22}\cell{Definition of group 17}\cell\row
\intbl{\b S23}\cell{Definition of group 18}\cell\row
\intbl{\b S24}\cell{Definition of group 19}\cell\row
\intbl{\b S25}\cell{Definition of group 20}\cell\row
\intbl{\b S26}\cell{Definition of group 21}\cell\row
\intbl{\b S27}\cell{Definition of group 22}\cell\row
\intbl{\b S28}\cell{Definition of group 23}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Slave and station status: 0 - good, 1 - bad}\cell\row\par
#108
\intbl{\b S1}\cell{Spare}\cell\row
\intbl{\b S2}\cell{Spare}\cell\row
\intbl{\b S3}\cell{Spare}\cell\row
\intbl{\b S4}\cell{Spare}\cell\row
\intbl{\b S5}\cell{Spare}\cell\row
\intbl{\b S6}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 18}\cell{Real}\cell{NVRAM memory utilization (percent)}\cell\row
\intbl{\b 19}\cell{Real}\cell{RAM memory utilization}\cell\row
\intbl{\b 20}\cell{-}\cell{Reserved}\cell\row
\intbl{\b 21}\cell{-}\cell{Reserved}\cell\row
\intbl{\b 22}\cell{-}\cell{Reserved}\cell\row
\intbl{\b 23}\cell{-}\cell{Reserved}\cell\row\par
#109
\intbl{\b S1}\cell{Expander bus slave address}\cell\row
\intbl{\b S2}\cell{Selected channel (1-8)}\cell\row
\intbl{\b S3}\cell{Pulse trigger level (0=low-high, 1=high-low)}\cell\row
\intbl{\b S4}\cell{Expected pulse duration range}\cell\row
\intbl{\b S5}\cell{Gain}\cell\row
\intbl{\b S6}\cell{High alarm value}\cell\row
\intbl{\b S7}\cell{Low alarm value}\cell\row
\intbl{\b S8}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is pulse duration times gain}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Pulse duration high alarm: 0 - no alarm, 1 - high alarm}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Pulse duration low alarm: 0 - no alarm, 1 - low alarm}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Slave communication status: 0 - good, 1 - no response, illegal response or pulse duration out of range}\cell\row\par
#110
\intbl{\b S1}\cell{Output override (0-normal 1-hold 2-zero 3-one)}\cell\row
\intbl{\b S2}\cell{Operation on input 1}\cell\row
\intbl{\b S3}\cell{Operation on input 2}\cell\row
\intbl{\b S4}\cell{Operation on input 3}\cell\row
\intbl{\b S5}\cell{Operation on input 4}\cell\row
\intbl{\b S6}\cell{Operation on input 5}\cell\row
\intbl{\b S7}\cell{Input 1}\cell\row
\intbl{\b S8}\cell{Input 2}\cell\row
\intbl{\b S9}\cell{Input 3}\cell\row
\intbl{\b S10}\cell{Input 4}\cell\row
\intbl{\b S11}\cell{Input 5}\cell\row
\par\sb120\li240{\fs25\b Format for S2 through S6}\par\pard
\par\sb80\li240\sa40{\b Operation}\par\pard
\trowd\trgaph240\trleft120\cellx960\cellx10080
\intbl{\b XX0}\cell{PUT value on top of stack}\cell\row
\intbl{\b XX1}\cell{AND value with value on top of stack}\cell\row
\intbl{\b XX2}\cell{OR value with value on top of stack}\cell\row
\par\sb80\li240\sa40{\b State of Input Acted On}\par\pard
\trowd\trgaph240\trleft120\cellx960\cellx10080
\intbl{\b X0X}\cell{use value from stack (0 or 1)}\cell\row
\intbl{\b X1X}\cell{use logical state of input (0 or 1)}\cell\row
\intbl{\b X2X}\cell{use inverted logical state of input (0 or 1)}\cell\row
\intbl{\b X3X}\cell{perform operation when input changes (from 0 to 1)}\cell\row
\intbl{\b X4X}\cell{perform operation when input changes (from 1 to 0)}\cell\row
\par\sb80\li240\sa40{\b Override Indicator}\par\pard
\trowd\trgaph240\trleft120\cellx960\cellx10080
\intbl{\b 0XX}\cell{no input override}\cell\row
\intbl{\b 1XX}\cell{force input to logic 1}\cell\row
\intbl{\b 2XX}\cell{force input to logic 0}\cell\row\par
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is ladder-logic function of inputs}\cell\row\par
#111
\intbl{\b S1}\cell{Output override (0-normal 1-hold 2-zero 3-one)}\cell\row
\intbl{\b S2}\cell{Operation on input 1}\cell\row
\intbl{\b S3}\cell{Operation on input 2}\cell\row
\intbl{\b S4}\cell{Operation on input 3}\cell\row
\intbl{\b S5}\cell{Operation on input 4}\cell\row
\intbl{\b S6}\cell{Operation on input 5}\cell\row
\intbl{\b S7}\cell{Operation on input 6}\cell\row
\intbl{\b S8}\cell{Operation on input 7}\cell\row
\intbl{\b S9}\cell{Operation on input 8}\cell\row
\intbl{\b S10}\cell{Operation on input 9}\cell\row
\intbl{\b S11}\cell{Operation on input 10}\cell\row
\intbl{\b S12}\cell{Input 1}\cell\row
\intbl{\b S13}\cell{Input 2}\cell\row
\intbl{\b S14}\cell{Input 3}\cell\row
\intbl{\b S15}\cell{Input 4}\cell\row
\intbl{\b S16}\cell{Input 5}\cell\row
\intbl{\b S17}\cell{Input 6}\cell\row
\intbl{\b S18}\cell{Input 7}\cell\row
\intbl{\b S19}\cell{Input 8}\cell\row
\intbl{\b S20}\cell{Input 9}\cell\row
\intbl{\b S21}\cell{Input 10}\cell\row
\par\sb120\li240{\fs25\b Format for S2 through S11}\par\pard
\par\sb80\li240\sa40{\b Operation}\par\pard
\trowd\trgaph240\trleft120\cellx960\cellx10080
\intbl{\b XX0}\cell{PUT value on top of stack}\cell\row
\intbl{\b XX1}\cell{AND value with value on top of stack}\cell\row
\intbl{\b XX2}\cell{OR value with value on top of stack}\cell\row
\par\sb80\li240\sa40{\b State of Input Acted On}\par\pard
\trowd\trgaph240\trleft120\cellx960\cellx10080
\intbl{\b X0X}\cell{use value from stack (0 or 1)}\cell\row
\intbl{\b X1X}\cell{use logical state of input (0 or 1)}\cell\row
\intbl{\b X2X}\cell{use inverted logical state of input (0 or 1)}\cell\row
\intbl{\b X3X}\cell{perform operation when input changes (from 0 to 1)}\cell\row
\intbl{\b X4X}\cell{perform operation when input changes (from 1 to 0)}\cell\row
\par\sb80\li240\sa40{\b Override Indicator}\par\pard
\trowd\trgaph240\trleft120\cellx960\cellx10080
\intbl{\b 0XX}\cell{no input override}\cell\row
\intbl{\b 1XX}\cell{force input to logic 1}\cell\row
\intbl{\b 2XX}\cell{force input to logic 0}\cell\row\par
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is ladder-logic function of inputs}\cell\row\par
#112
\intbl{\b S1}\cell{Output override (0-normal 1-hold 2-zero 3-one)}\cell\row
\intbl{\b S2}\cell{Operation on input 1}\cell\row
\intbl{\b S3}\cell{Operation on input 2}\cell\row
\intbl{\b S4}\cell{Operation on input 3}\cell\row
\intbl{\b S5}\cell{Operation on input 4}\cell\row
\intbl{\b S6}\cell{Operation on input 5}\cell\row
\intbl{\b S7}\cell{Operation on input 6}\cell\row
\intbl{\b S8}\cell{Operation on input 7}\cell\row
\intbl{\b S9}\cell{Operation on input 8}\cell\row
\intbl{\b S10}\cell{Operation on input 9}\cell\row
\intbl{\b S11}\cell{Operation on input 10}\cell\row
\intbl{\b S12}\cell{Operation on input 11}\cell\row
\intbl{\b S13}\cell{Operation on input 12}\cell\row
\intbl{\b S14}\cell{Operation on input 13}\cell\row
\intbl{\b S15}\cell{Operation on input 14}\cell\row
\intbl{\b S16}\cell{Operation on input 15}\cell\row
\intbl{\b S17}\cell{Operation on input 16}\cell\row
\intbl{\b S18}\cell{Operation on input 17}\cell\row
\intbl{\b S19}\cell{Operation on input 18}\cell\row
\intbl{\b S20}\cell{Operation on input 19}\cell\row
\intbl{\b S21}\cell{Operation on input 20}\cell\row
\intbl{\b S22}\cell{Input 1}\cell\row
\intbl{\b S23}\cell{Input 2}\cell\row
\intbl{\b S24}\cell{Input 3}\cell\row
\intbl{\b S25}\cell{Input 4}\cell\row
\intbl{\b S26}\cell{Input 5}\cell\row
\intbl{\b S27}\cell{Input 6}\cell\row
\intbl{\b S28}\cell{Input 7}\cell\row
\intbl{\b S29}\cell{Input 8}\cell\row
\intbl{\b S30}\cell{Input 9}\cell\row
\intbl{\b S31}\cell{Input 10}\cell\row
\intbl{\b S32}\cell{Input 11}\cell\row
\intbl{\b S33}\cell{Input 12}\cell\row
\intbl{\b S34}\cell{Input 13}\cell\row
\intbl{\b S35}\cell{Input 14}\cell\row
\intbl{\b S36}\cell{Input 15}\cell\row
\intbl{\b S37}\cell{Input 16}\cell\row
\intbl{\b S38}\cell{Input 17}\cell\row
\intbl{\b S39}\cell{Input 18}\cell\row
\intbl{\b S40}\cell{Input 19}\cell\row
\intbl{\b S41}\cell{Input 20}\cell\row
\par\sb120\li240{\fs25\b Format for S2 through S21}\par\pard
\par\sb80\li240\sa40{\b Operation}\par\pard
\trowd\trgaph240\trleft120\cellx960\cellx10080
\intbl{\b XX0}\cell{PUT value on top of stack}\cell\row
\intbl{\b XX1}\cell{AND value with value on top of stack}\cell\row
\intbl{\b XX2}\cell{OR value with value on top of stack}\cell\row
\par\sb80\li240\sa40{\b State of Input Acted On}\par\pard
\trowd\trgaph240\trleft120\cellx960\cellx10080
\intbl{\b X0X}\cell{use value from stack (0 or 1)}\cell\row
\intbl{\b X1X}\cell{use logical state of input (0 or 1)}\cell\row
\intbl{\b X2X}\cell{use inverted logical state of input (0 or 1)}\cell\row
\intbl{\b X3X}\cell{perform operation when input changes (from 0 to 1)}\cell\row
\intbl{\b X4X}\cell{perform operation when input changes (from 1 to 0)}\cell\row
\par\sb80\li240\sa40{\b Override Indicator}\par\pard
\trowd\trgaph240\trleft120\cellx960\cellx10080
\intbl{\b 0XX}\cell{no input override}\cell\row
\intbl{\b 1XX}\cell{force input to logic 1}\cell\row
\intbl{\b 2XX}\cell{force input to logic 0}\cell\row\par
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is ladder-logic function of inputs}\cell\row\par
#113
\intbl{\b S1}\cell{Next block in link list}\cell\row
\intbl{\b S2}\cell{Identification number}\cell\row
\intbl{\b S3}\cell{ASCII character number 1}\cell\row
\intbl{\b S4}\cell{ASCII character number 2}\cell\row
\intbl{\b S5}\cell{ASCII character number 3}\cell\row
\intbl{\b S6}\cell{ASCII character number 4}\cell\row
\intbl{\b S7}\cell{ASCII character number 5}\cell\row
\intbl{\b S8}\cell{ASCII character number 6}\cell\row
\intbl{\b S9}\cell{ASCII character number 7}\cell\row
\intbl{\b S10}\cell{ASCII character number 8}\cell\row
\intbl{\b S11}\cell{ASCII character number 9}\cell\row
\intbl{\b S12}\cell{ASCII character number 10}\cell\row
\intbl{\b S13}\cell{ASCII character number 11}\cell\row
\intbl{\b S14}\cell{ASCII character number 12}\cell\row
\intbl{\b S15}\cell{ASCII character number 13}\cell\row
\intbl{\b S16}\cell{ASCII character number 14}\cell\row
\intbl{\b S17}\cell{ASCII character number 15}\cell\row
\intbl{\b S18}\cell{ASCII character number 16}\cell\row
\intbl{\b S19}\cell{ASCII character number 17}\cell\row
\intbl{\b S20}\cell{ASCII character number 18}\cell\row
\intbl{\b S21}\cell{ASCII character number 19}\cell\row
\intbl{\b S22}\cell{ASCII character number 20}\cell\row
\intbl{\b S23}\cell{ASCII character number 21}\cell\row
\intbl{\b S24}\cell{ASCII character number 22}\cell\row
\intbl{\b S25}\cell{ASCII character number 23}\cell\row
\intbl{\b S26}\cell{ASCII character number 24}\cell\row
\intbl{\b S27}\cell{ASCII character number 25}\cell\row
\intbl{\b S28}\cell{ASCII character number 26}\cell\row
\intbl{\b S29}\cell{ASCII character number 27}\cell\row
\intbl{\b S30}\cell{ASCII character number 28}\cell\row
\intbl{\b S31}\cell{ASCII character number 29}\cell\row
\intbl{\b S32}\cell{ASCII character number 30}\cell\row
\intbl{\b S33}\cell{ASCII character number 31}\cell\row
\intbl{\b S34}\cell{ASCII character number 32}\cell\row
\intbl{\b S35}\cell{ASCII character number 33}\cell\row
\intbl{\b S36}\cell{ASCII character number 34}\cell\row
\intbl{\b S37}\cell{ASCII character number 35}\cell\row
\intbl{\b S38}\cell{ASCII character number 36}\cell\row
\intbl{\b S39}\cell{ASCII character number 37}\cell\row
\intbl{\b S40}\cell{ASCII character number 38}\cell\row
\intbl{\b S41}\cell{ASCII character number 39}\cell\row
\intbl{\b S42}\cell{ASCII character number 40}\cell\row
\intbl{\b S43}\cell{ASCII character number 41}\cell\row
\intbl{\b S44}\cell{ASCII character number 42}\cell\row
\intbl{\b S45}\cell{ASCII character number 43}\cell\row
\intbl{\b S46}\cell{ASCII character number 44}\cell\row
\intbl{\b S47}\cell{ASCII character number 45}\cell\row
\intbl{\b S48}\cell{ASCII character number 46}\cell\row
\intbl{\b S49}\cell{ASCII character number 47}\cell\row
\intbl{\b S50}\cell{ASCII character number 48}\cell\row
\intbl{\b S51}\cell{ASCII character number 49}\cell\row
\intbl{\b S52}\cell{ASCII character number 50}\cell\row
\intbl{\b S53}\cell{ASCII character number 51}\cell\row
\intbl{\b S54}\cell{ASCII character number 52}\cell\row
\intbl{\b S55}\cell{ASCII character number 53}\cell\row
\intbl{\b S56}\cell{ASCII character number 54}\cell\row
\intbl{\b S57}\cell{ASCII character number 55}\cell\row
\intbl{\b S58}\cell{ASCII character number 56}\cell\row
\intbl{\b S59}\cell{ASCII character number 57}\cell\row
\intbl{\b S60}\cell{ASCII character number 58}\cell\row
\intbl{\b S61}\cell{ASCII character number 59}\cell\row
\intbl{\b S62}\cell{ASCII character number 60}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Reserved}\cell\row\par
#114
\intbl{\b S1}\cell{Expander bus slave address (0-63)}\cell\row
\intbl{\b S2}\cell{Starting zone number of one's digit (1-4)}\cell\row
\intbl{\b S3}\cell{Action on slave failure (0=trip 1=continue)}\cell\row
\intbl{\b S4}\cell{Number of digits (1-4)}\cell\row
\intbl{\b S5}\cell{Gain}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is value times gain}\cell\row\par
#115
\intbl{\b S1}\cell{Expander bus slave address (0-63)}\cell\row
\intbl{\b S2}\cell{Slave def=hold+type+grp}\cell\row
\intbl{\b S3}\cell{Action on slave failure (0=trip 1=continue)}\cell\row
\intbl{\b S4}\cell{Input value}\cell\row
\intbl{\b S5}\cell{Gain for input value}\cell\row
\intbl{\b S6}\cell{Number of BCD digits (2 or 4)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Slave status: 0 - good, 1 - bad}\cell\row\par
#116
\intbl{\b S1}\cell{Control signal}\cell\row
\intbl{\b S2}\cell{Destination}\cell\row
\intbl{\b S3}\cell{Function (0=jump 1=MCR)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is value of S1}\cell\row\par
#117
\intbl{\b S1}\cell{Boolean value of parameter 0}\cell\row
\intbl{\b S2}\cell{Boolean value of parameter 1}\cell\row
\intbl{\b S3}\cell{Boolean value of parameter 2}\cell\row
\intbl{\b S4}\cell{Boolean value of parameter 3}\cell\row
\intbl{\b S5}\cell{Boolean value of parameter 4}\cell\row
\intbl{\b S6}\cell{Boolean value of parameter 5}\cell\row
\intbl{\b S7}\cell{Boolean value of parameter 6}\cell\row
\intbl{\b S8}\cell{Boolean value of parameter 7}\cell\row
\intbl{\b S9}\cell{Boolean value of parameter 8}\cell\row
\intbl{\b S10}\cell{Boolean value of parameter 9}\cell\row
\intbl{\b S11}\cell{Selection signal}\cell\row
\intbl{\b S12}\cell{Link to next slave block (0 = end)}\cell\row
\intbl{\b S13}\cell{Edit signal}\cell\row
\intbl{\b S14}\cell{Edit parameter select}\cell\row
\intbl{\b S15}\cell{Edit value}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is parameter value selected.}\cell\row\par
#118
\intbl{\b S1}\cell{Real value of parameter 0}\cell\row
\intbl{\b S2}\cell{Real value of parameter 1}\cell\row
\intbl{\b S3}\cell{Real value of parameter 2}\cell\row
\intbl{\b S4}\cell{Real value of parameter 3}\cell\row
\intbl{\b S5}\cell{Real value of parameter 4}\cell\row
\intbl{\b S6}\cell{Real value of parameter 5}\cell\row
\intbl{\b S7}\cell{Real value of parameter 6}\cell\row
\intbl{\b S8}\cell{Real value of parameter 7}\cell\row
\intbl{\b S9}\cell{Real value of parameter 8}\cell\row
\intbl{\b S10}\cell{Real value of parameter 9}\cell\row
\intbl{\b S11}\cell{Selection signal}\cell\row
\intbl{\b S12}\cell{Link to next slave block (0 = end)}\cell\row
\intbl{\b S13}\cell{Edit signal}\cell\row
\intbl{\b S14}\cell{Edit parameter select}\cell\row
\intbl{\b S15}\cell{Edit value}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is parameter value selected.}\cell\row\par
#119
\intbl{\b S1}\cell{Input 0}\cell\row
\intbl{\b S2}\cell{Input 1}\cell\row
\intbl{\b S3}\cell{Input 2}\cell\row
\intbl{\b S4}\cell{Input 3}\cell\row
\intbl{\b S5}\cell{Input 4}\cell\row
\intbl{\b S6}\cell{Input 5}\cell\row
\intbl{\b S7}\cell{Input 6}\cell\row
\intbl{\b S8}\cell{Input 7}\cell\row
\intbl{\b S9}\cell{Input 8}\cell\row
\intbl{\b S10}\cell{Input 9}\cell\row
\intbl{\b S11}\cell{Selection signal}\cell\row
\intbl{\b S12}\cell{Link to next block number}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is input value selected}\cell\row\par
#120
\intbl{\b S1}\cell{Input 0}\cell\row
\intbl{\b S2}\cell{Input 1}\cell\row
\intbl{\b S3}\cell{Input 2}\cell\row
\intbl{\b S4}\cell{Input 3}\cell\row
\intbl{\b S5}\cell{Input 4}\cell\row
\intbl{\b S6}\cell{Input 5}\cell\row
\intbl{\b S7}\cell{Input 6}\cell\row
\intbl{\b S8}\cell{Input 7}\cell\row
\intbl{\b S9}\cell{Input 8}\cell\row
\intbl{\b S10}\cell{Input 9}\cell\row
\intbl{\b S11}\cell{Selection signal}\cell\row
\intbl{\b S12}\cell{Link to next block number}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is input value selected}\cell\row\par
#121
\intbl{\b S1}\cell{Source module address}\cell\row
\intbl{\b S2}\cell{Source block address}\cell\row
\intbl{\b S3}\cell{Requested PCU address}\cell\row
\intbl{\b S4}\cell{Requested loop address}\cell\row
\intbl{\b S5}\cell{Spare 1}\cell\row
\intbl{\b S6}\cell{Spare 2}\cell\row
\intbl{\b S7}\cell{Spare integer input}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is analog input value with quality and alarm state}\cell\row\par
#122
\intbl{\b S1}\cell{Source module address}\cell\row
\intbl{\b S2}\cell{Source block address}\cell\row
\intbl{\b S3}\cell{Requested PCU address}\cell\row
\intbl{\b S4}\cell{Requested loop address}\cell\row
\intbl{\b S5}\cell{Spare 1}\cell\row
\intbl{\b S6}\cell{Spare 2}\cell\row
\intbl{\b S7}\cell{Spare 3}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is digital input value with quality and alarm state}\cell\row\par
#123
\intbl{\b S1}\cell{Control input}\cell\row
\intbl{\b S2}\cell{Feedback input 1}\cell\row
\intbl{\b S3}\cell{Feedback input 2}\cell\row
\intbl{\b S4}\cell{Control output status override}\cell\row
\intbl{\b S5}\cell{Output override permissive}\cell\row
\intbl{\b S6}\cell{Override output}\cell\row
\intbl{\b S7}\cell{Feedback status mask (output = 0)}\cell\row
\intbl{\b S8}\cell{Feedback status mask (output = 1)}\cell\row
\intbl{\b S9}\cell{Feedback wait time (seconds)}\cell\row
\intbl{\b S10}\cell{Device driver display type}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is control output}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Control output status: 0.0 - good, 1.0 - bad, 2.0 - waiting}\cell\row\par
#124
\intbl{\b S1}\cell{Next sequence monitor block}\cell\row
\intbl{\b S2}\cell{Control status input}\cell\row
\intbl{\b S3}\cell{Step trigger}\cell\row
\intbl{\b S4}\cell{Hold/initialize}\cell\row
\intbl{\b S5}\cell{Semi-auto trigger}\cell\row
\intbl{\b S6}\cell{Emergency stop}\cell\row
\intbl{\b S7}\cell{Initial step number}\cell\row
\intbl{\b S8}\cell{Semi-auto permissive}\cell\row
\intbl{\b S9}\cell{Step type number 1}\cell\row
\intbl{\b S10}\cell{Step type number 2}\cell\row
\intbl{\b S11}\cell{Step type number 3}\cell\row
\intbl{\b S12}\cell{Step type number 4}\cell\row
\intbl{\b S13}\cell{Step type number 5}\cell\row
\intbl{\b S14}\cell{Step type number 6}\cell\row
\intbl{\b S15}\cell{Step type number 7}\cell\row
\intbl{\b S16}\cell{Step type number 8}\cell\row
\intbl{\b S17}\cell{Normal step number 1}\cell\row
\intbl{\b S18}\cell{Normal step number 2}\cell\row
\intbl{\b S19}\cell{Normal step number 3}\cell\row
\intbl{\b S20}\cell{Normal step number 4}\cell\row
\intbl{\b S21}\cell{Normal step number 5}\cell\row
\intbl{\b S22}\cell{Normal step number 6}\cell\row
\intbl{\b S23}\cell{Normal step number 7}\cell\row
\intbl{\b S24}\cell{Normal step number 8}\cell\row
\intbl{\b S25}\cell{Fault step number 1}\cell\row
\intbl{\b S26}\cell{Fault step number 2}\cell\row
\intbl{\b S27}\cell{Fault step number 3}\cell\row
\intbl{\b S28}\cell{Fault step number 4}\cell\row
\intbl{\b S29}\cell{Fault step number 5}\cell\row
\intbl{\b S30}\cell{Fault step number 6}\cell\row
\intbl{\b S31}\cell{Fault step number 7}\cell\row
\intbl{\b S32}\cell{Fault step number 8}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is jump step number}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Output is jump step trigger}\cell\row\par
#125
\intbl{\b S1}\cell{Block address control output status 1}\cell\row
\intbl{\b S2}\cell{Block address control output status 2}\cell\row
\intbl{\b S3}\cell{Block address control output status 3}\cell\row
\intbl{\b S4}\cell{Block address control output status 4}\cell\row
\intbl{\b S5}\cell{Block address control output status 5}\cell\row
\intbl{\b S6}\cell{Block address control output status 6}\cell\row
\intbl{\b S7}\cell{Block address control output status 7}\cell\row
\intbl{\b S8}\cell{Block address control output status 8}\cell\row
\intbl{\b S9}\cell{Block address control output status 9}\cell\row
\intbl{\b S10}\cell{Block address control output status 10}\cell\row
\intbl{\b S11}\cell{Block address control output status 11}\cell\row
\intbl{\b S12}\cell{Block address control output status 12}\cell\row
\intbl{\b S13}\cell{Block address control output status 13}\cell\row
\intbl{\b S14}\cell{Block address control output status 14}\cell\row
\intbl{\b S15}\cell{Block address control output status 15}\cell\row
\intbl{\b S16}\cell{Block address control output status 16}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Control output status: 0.0 - good, 1.0 - bad, 2.0 - waiting}\cell\row\par
#126
\intbl{\b S1}\cell{Select input}\cell\row
\intbl{\b S2}\cell{Conversion type}\cell\row
\intbl{\b S3}\cell{Link to next slave block}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output 0 (least significant bit)}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Output 1}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Output 2}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Output 3}\cell\row
\intbl{\b N+4}\cell{Bit}\cell{Output 4}\cell\row
\intbl{\b N+5}\cell{Bit}\cell{Output 5}\cell\row
\intbl{\b N+6}\cell{Bit}\cell{Output 6}\cell\row
\intbl{\b N+7}\cell{Bit}\cell{Output 7 (most significant bit)}\cell\row\par
#127
\intbl{\b S1}\cell{Definition of node number 1}\cell\row
\intbl{\b S2}\cell{Definition of node number 2}\cell\row
\intbl{\b S3}\cell{Definition of node number 3}\cell\row
\intbl{\b S4}\cell{Definition of node number 4}\cell\row
\intbl{\b S5}\cell{Definition of node number 5}\cell\row
\intbl{\b S6}\cell{Definition of node number 6}\cell\row
\intbl{\b S7}\cell{Definition of node number 7}\cell\row
\intbl{\b S8}\cell{Definition of node number 8}\cell\row
\intbl{\b S9}\cell{Definition of node number 9}\cell\row
\intbl{\b S10}\cell{Definition of node number 10}\cell\row
\intbl{\b S11}\cell{Definition of node number 11}\cell\row
\intbl{\b S12}\cell{Definition of node number 12}\cell\row
\intbl{\b S13}\cell{Definition of node number 13}\cell\row
\intbl{\b S14}\cell{Definition of node number 14}\cell\row
\intbl{\b S15}\cell{Definition of node number 15}\cell\row
\intbl{\b S16}\cell{Definition of node number 16}\cell\row
\intbl{\b S17}\cell{Definition of node number 17}\cell\row
\intbl{\b S18}\cell{Definition of node number 18}\cell\row
\intbl{\b S19}\cell{Definition of node number 19}\cell\row
\intbl{\b S20}\cell{Definition of node number 20}\cell\row
\intbl{\b S21}\cell{Definition of node number 21}\cell\row
\intbl{\b S22}\cell{Definition of node number 22}\cell\row
\intbl{\b S23}\cell{Definition of node number 23}\cell\row
\intbl{\b S24}\cell{Definition of node number 24}\cell\row
\intbl{\b S25}\cell{Definition of node number 25}\cell\row
\intbl{\b S26}\cell{Definition of node number 26}\cell\row
\intbl{\b S27}\cell{Definition of node number 27}\cell\row
\intbl{\b S28}\cell{Definition of node number 28}\cell\row
\intbl{\b S29}\cell{Definition of node number 29}\cell\row
\intbl{\b S30}\cell{Definition of node number 30}\cell\row
\intbl{\b S31}\cell{Definition of node number 31}\cell\row
\intbl{\b S32}\cell{Definition of node number 32}\cell\row
\intbl{\b S33}\cell{Definition of node number 33}\cell\row
\intbl{\b S34}\cell{Definition of node number 34}\cell\row
\intbl{\b S35}\cell{Definition of node number 35}\cell\row
\intbl{\b S36}\cell{Definition of node number 36}\cell\row
\intbl{\b S37}\cell{Definition of node number 37}\cell\row
\intbl{\b S38}\cell{Definition of node number 38}\cell\row
\intbl{\b S39}\cell{Definition of node number 39}\cell\row
\intbl{\b S40}\cell{Definition of node number 40}\cell\row
\intbl{\b S41}\cell{Definition of node number 41}\cell\row
\intbl{\b S42}\cell{Definition of node number 42}\cell\row
\intbl{\b S43}\cell{Definition of node number 43}\cell\row
\intbl{\b S44}\cell{Definition of node number 44}\cell\row
\intbl{\b S45}\cell{Definition of node number 45}\cell\row
\intbl{\b S46}\cell{Definition of node number 46}\cell\row
\intbl{\b S47}\cell{Definition of node number 47}\cell\row
\intbl{\b S48}\cell{Definition of node number 48}\cell\row
\intbl{\b S49}\cell{Definition of node number 49}\cell\row
\intbl{\b S50}\cell{Definition of node number 50}\cell\row
\intbl{\b S51}\cell{Definition of node number 51}\cell\row
\intbl{\b S52}\cell{Definition of node number 52}\cell\row
\intbl{\b S53}\cell{Definition of node number 53}\cell\row
\intbl{\b S54}\cell{Definition of node number 54}\cell\row
\intbl{\b S55}\cell{Definition of node number 55}\cell\row
\intbl{\b S56}\cell{Definition of node number 56}\cell\row
\intbl{\b S57}\cell{Definition of node number 57}\cell\row
\intbl{\b S58}\cell{Definition of node number 58}\cell\row
\intbl{\b S59}\cell{Definition of node number 59}\cell\row
\intbl{\b S60}\cell{Definition of node number 60}\cell\row
\intbl{\b S61}\cell{Definition of node number 61}\cell\row
\intbl{\b S62}\cell{Definition of node number 62}\cell\row
\intbl{\b S63}\cell{Definition of node number 63}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 7}\cell{Integer}\cell{Spare}\cell\row\par
#128
\intbl{\b S1}\cell{Output slave function block number 1}\cell\row
\intbl{\b S2}\cell{Group A default output number 1}\cell\row
\intbl{\b S3}\cell{Group A default output number 2}\cell\row
\intbl{\b S4}\cell{Group A default output number 3}\cell\row
\intbl{\b S5}\cell{Group A default output number 4}\cell\row
\intbl{\b S6}\cell{Group A default output number 5}\cell\row
\intbl{\b S7}\cell{Group A default output number 6}\cell\row
\intbl{\b S8}\cell{Group A default output number 7}\cell\row
\intbl{\b S9}\cell{Group A default output number 8}\cell\row
\intbl{\b S10}\cell{Group B default output number 1}\cell\row
\intbl{\b S11}\cell{Group B default output number 2}\cell\row
\intbl{\b S12}\cell{Group B default output number 3}\cell\row
\intbl{\b S13}\cell{Group B default output number 4}\cell\row
\intbl{\b S14}\cell{Group B default output number 5}\cell\row
\intbl{\b S15}\cell{Group B default output number 6}\cell\row
\intbl{\b S16}\cell{Group B default output number 7}\cell\row
\intbl{\b S17}\cell{Group B default output number 8}\cell\row
\intbl{\b S18}\cell{Output slave function block number 2}\cell\row
\intbl{\b S19}\cell{Group A default output number 1}\cell\row
\intbl{\b S20}\cell{Group A default output number 2}\cell\row
\intbl{\b S21}\cell{Group A default output number 3}\cell\row
\intbl{\b S22}\cell{Group A default output number 4}\cell\row
\intbl{\b S23}\cell{Group A default output number 5}\cell\row
\intbl{\b S24}\cell{Group A default output number 6}\cell\row
\intbl{\b S25}\cell{Group A default output number 7}\cell\row
\intbl{\b S26}\cell{Group A default output number 8}\cell\row
\intbl{\b S27}\cell{Group B default output number 1}\cell\row
\intbl{\b S28}\cell{Group B default output number 2}\cell\row
\intbl{\b S29}\cell{Group B default output number 3}\cell\row
\intbl{\b S30}\cell{Group B default output number 4}\cell\row
\intbl{\b S31}\cell{Group B default output number 5}\cell\row
\intbl{\b S32}\cell{Group B default output number 6}\cell\row
\intbl{\b S33}\cell{Group B default output number 7}\cell\row
\intbl{\b S34}\cell{Group B default output number 8}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{No output }\cell\row\par
#129
\intbl{\b S1}\cell{Control input 1}\cell\row
\intbl{\b S2}\cell{Control input 2}\cell\row
\intbl{\b S3}\cell{Feedback 1}\cell\row
\intbl{\b S4}\cell{Feedback 2}\cell\row
\intbl{\b S5}\cell{Feedback 3}\cell\row
\intbl{\b S6}\cell{Feedback 4}\cell\row
\intbl{\b S7}\cell{Default mask}\cell\row
\intbl{\b S8}\cell{Output mask number 1}\cell\row
\intbl{\b S9}\cell{Output mask number 2}\cell\row
\intbl{\b S10}\cell{Output mask number 3}\cell\row
\intbl{\b S11}\cell{Feedback for output mask number 1}\cell\row
\intbl{\b S12}\cell{Feedback for output mask number 2}\cell\row
\intbl{\b S13}\cell{Feedback for output mask number 3}\cell\row
\intbl{\b S14}\cell{Control output status override (see below)}\cell\row
\intbl{\b S15}\cell{Manual mode permissive (0=off 1=on)}\cell\row
\intbl{\b S16}\cell{Feedback wait time (seconds)}\cell\row
\intbl{\b S17}\cell{Fault wait time}\cell\row
\intbl{\b S18}\cell{Device driver display type}\cell\row
\intbl{\b S19}\cell{Next allowable mask number for output mask 1 in manual mode}\cell\row
\intbl{\b S20}\cell{Next allowable mask number for output mask 2 in manual mode}\cell\row
\intbl{\b S21}\cell{Next allowable mask number for output mask 3 in manual mode}\cell\row
\intbl{\b S22}\cell{Pulsed outputs length (0 = outputs latched)}\cell\row
\intbl{\b S23}\cell{Initial mode (0=manual 1=auto)}\cell\row
\intbl{\b S24}\cell{Startup track flag (0-do not track , 1-track during startup)}\cell\row
\intbl{\b S25}\cell{Control override}\cell\row
\par\sb120\li240{\fs25\b Format for S14}\par\pard
\par\sb80\li240\sa40{\b Status override}\par\pard
\trowd\trgaph240\trleft120\cellx960\cellx10080
\intbl{\b XX0}\cell{none}\cell\row
\intbl{\b XX1}\cell{output status}\cell\row
\intbl{\b XX2}\cell{output status and alarm}\cell\row
\par\sb80\li240\sa40{\b Control override}\par\pard
\trowd\trgaph240\trleft120\cellx960\cellx10080
\intbl{\b X0X}\cell{go to manual mode and default control outputs}\cell\row
\intbl{\b X1X}\cell{hold current mode and control outputs}\cell\row
\intbl{\b X2X}\cell{go to manual mode and hold current control outputs}\cell\row
\intbl{\b X3X}\cell{go to auto mode and set outputs as selected by current control inputs}\cell\row
\intbl{\b X4X}\cell{go to manual mode and set outputs as selected by operator interface device}\cell\row
\par\sb80\li240\sa40{\b Operation}\par\pard
\trowd\trgaph240\trleft120\cellx960\cellx10080
\intbl{\b 0XX}\cell{normal operation}\cell\row
\intbl{\b 1XX}\cell{early good status enable}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is control output 1}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Output is control output 2}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Output is control output 3}\cell\row
\intbl{\b N+3}\cell{Real}\cell{Control output status: 0.0 - good, 1.0 - bad, 2.0 - waiting}\cell\row\par
#130
\intbl{\b S1}\cell{Configuration lock/1=lock 0=unlock}\cell\row
\intbl{\b S2}\cell{Address of remote loop for tuning and configuration}\cell\row
\intbl{\b S3}\cell{Address of remote PCU for tuning and configuration}\cell\row
\intbl{\b S4}\cell{Address of remote module for tuning and configuration}\cell\row
\intbl{\b S5}\cell{Port 0 command/reply delay after transmitter turned on (msec)}\cell\row
\intbl{\b S6}\cell{Port 0 transmitter turn off delay after command/reply sent (msec)}\cell\row
\intbl{\b S7}\cell{Port 1 command/reply delay after transmitter turned on (msec)}\cell\row
\intbl{\b S8}\cell{Port 1 transmitter turn off delay after command/reply sent (msec)}\cell\row
\intbl{\b S9}\cell{Maximum exception report timer (0-255 secs)}\cell\row
\intbl{\b S10}\cell{Communication status watchdog timer (seconds)}\cell\row
\intbl{\b S11}\cell{Action on communication equipment failure}\cell\row
\intbl{\b S12}\cell{Communication retry count}\cell\row
\intbl{\b S13}\cell{Port data characteristics}\cell\row
\intbl{\b S14}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 1}\cell{Bit}\cell{Port 0 communication status: 0 - good, 1 - alarm}\cell\row
\intbl{\b 2}\cell{Bit}\cell{Port 1 communication status: 0 - good, 1 - alarm}\cell\row
\intbl{\b 3}\cell{Integer}\cell{Output is number of exception reports per second}\cell\row
\intbl{\b 4}\cell{Integer}\cell{Output is average number of exception reports per second}\cell\row
\intbl{\b 5}\cell{Integer}\cell{Output is maximum number of exception reports per second}\cell\row
\intbl{\b 6}\cell{Integer}\cell{Reserved}\cell\row\par
#131
\intbl{\b S1}\cell{Exception report (0=from/1=to) other gate}\cell\row
\intbl{\b S2}\cell{Loop address providing exception report}\cell\row
\intbl{\b S3}\cell{Exception report data type}\cell\row
\intbl{\b S4}\cell{Exception report PCU address}\cell\row
\intbl{\b S5}\cell{Exception report module address}\cell\row
\intbl{\b S6}\cell{Exception report block address}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Integer}\cell{Output indicates status of data with quality}\cell\row\par
#132
\intbl{\b S1}\cell{Slave address}\cell\row
\intbl{\b S2}\cell{Block address of next analog input/slave}\cell\row
\intbl{\b S3}\cell{Continue on slave error}\cell\row
\intbl{\b S4}\cell{Signal type of input 1}\cell\row
\intbl{\b S5}\cell{Engineering units zero of input 1}\cell\row
\intbl{\b S6}\cell{Engineering units span of input 1}\cell\row
\intbl{\b S7}\cell{Signal type of input 2}\cell\row
\intbl{\b S8}\cell{Engineering units zero of input 2}\cell\row
\intbl{\b S9}\cell{Engineering units span of input 2}\cell\row
\intbl{\b S10}\cell{Signal type of input 3}\cell\row
\intbl{\b S11}\cell{Engineering units zero of input 3}\cell\row
\intbl{\b S12}\cell{Engineering units span of input 3}\cell\row
\intbl{\b S13}\cell{Signal type of input 4}\cell\row
\intbl{\b S14}\cell{Engineering units zero of input 4}\cell\row
\intbl{\b S15}\cell{Engineering units span of input 4}\cell\row
\intbl{\b S16}\cell{Signal type of input 5}\cell\row
\intbl{\b S17}\cell{Engineering units zero of input 5}\cell\row
\intbl{\b S18}\cell{Engineering units span of input 5}\cell\row
\intbl{\b S19}\cell{Spare}\cell\row
\intbl{\b S20}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is analog input 1}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is analog input 2}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is analog input 3}\cell\row
\intbl{\b N+3}\cell{Real}\cell{Output is analog input 4}\cell\row
\intbl{\b N+4}\cell{Real}\cell{Output is analog input 5}\cell\row
\intbl{\b N+5}\cell{Bit}\cell{Slave status: 0 - good, 1 - bad}\cell\row\par
#133
\intbl{\b S1}\cell{Block address transmitter input}\cell\row
\intbl{\b S2}\cell{Transmitter definition}\cell\row
\intbl{\b S3}\cell{Transmitter engineering units}\cell\row
\intbl{\b S4}\cell{Damping time in secs}\cell\row
\intbl{\b S5}\cell{Mode definitions}\cell\row
\intbl{\b S6}\cell{Operation select}\cell\row
\intbl{\b S7}\cell{Trigger}\cell\row
\intbl{\b S8}\cell{Percent of fixed output}\cell\row
\intbl{\b S9}\cell{Temperature compensation (TBN) offline/online}\cell\row
\intbl{\b S10}\cell{Transmitter output definition}\cell\row
\intbl{\b S11}\cell{Reserved}\cell\row
\intbl{\b S12}\cell{Transmitter address}\cell\row
\intbl{\b S13}\cell{Transmitter lower range}\cell\row
\intbl{\b S14}\cell{Transmitter upper range}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Transmitter status: 0 - good, 1 - bad}\cell\row\par
#134
\intbl{\b S1}\cell{Block number of next multi-sequence monitor}\cell\row
\intbl{\b S2}\cell{Control status input}\cell\row
\intbl{\b S3}\cell{Step trigger}\cell\row
\intbl{\b S4}\cell{Emergency stop}\cell\row
\intbl{\b S5}\cell{Hold/resume}\cell\row
\intbl{\b S6}\cell{Semi-auto permissive}\cell\row
\intbl{\b S7}\cell{Semi-auto trigger}\cell\row
\intbl{\b S8}\cell{Insert trigger}\cell\row
\intbl{\b S9}\cell{Resume phase number}\cell\row
\intbl{\b S10}\cell{Insert step number}\cell\row
\intbl{\b S11}\cell{Insert recipe number}\cell\row
\intbl{\b S12}\cell{Spare}\cell\row
\intbl{\b S13}\cell{Block address step type phase 1}\cell\row
\intbl{\b S14}\cell{Block address step type phase 2}\cell\row
\intbl{\b S15}\cell{Block address step type phase 3}\cell\row
\intbl{\b S16}\cell{Block address step type phase 4}\cell\row
\intbl{\b S17}\cell{Block address step type phase 5}\cell\row
\intbl{\b S18}\cell{Block address step type phase 6}\cell\row
\intbl{\b S19}\cell{Block address step type phase 7}\cell\row
\intbl{\b S20}\cell{Block address step type phase 8}\cell\row
\intbl{\b S21}\cell{Block address normal step phase 1}\cell\row
\intbl{\b S22}\cell{Block address normal step phase 2}\cell\row
\intbl{\b S23}\cell{Block address normal step phase 3}\cell\row
\intbl{\b S24}\cell{Block address normal step phase 4}\cell\row
\intbl{\b S25}\cell{Block address normal step phase 5}\cell\row
\intbl{\b S26}\cell{Block address normal step phase 6}\cell\row
\intbl{\b S27}\cell{Block address normal step phase 7}\cell\row
\intbl{\b S28}\cell{Block address normal step phase 8}\cell\row
\intbl{\b S29}\cell{Block address fault phase 1}\cell\row
\intbl{\b S30}\cell{Block address fault phase 2}\cell\row
\intbl{\b S31}\cell{Block address fault phase 3}\cell\row
\intbl{\b S32}\cell{Block address fault phase 4}\cell\row
\intbl{\b S33}\cell{Block address fault phase 5}\cell\row
\intbl{\b S34}\cell{Block address fault phase 6}\cell\row
\intbl{\b S35}\cell{Block address fault phase 7}\cell\row
\intbl{\b S36}\cell{Block address fault phase 8}\cell\row
\intbl{\b S37}\cell{Block address recipe value phase 1}\cell\row
\intbl{\b S38}\cell{Block address recipe value phase 2}\cell\row
\intbl{\b S39}\cell{Block address recipe value phase 3}\cell\row
\intbl{\b S40}\cell{Block address recipe value phase 4}\cell\row
\intbl{\b S41}\cell{Block address recipe value phase 5}\cell\row
\intbl{\b S42}\cell{Block address recipe value phase 6}\cell\row
\intbl{\b S43}\cell{Block address recipe value phase 7}\cell\row
\intbl{\b S44}\cell{Block address recipe value phase 8}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is jump step number}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Output is jump step trigger}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is jump step recipe value}\cell\row
\intbl{\b N+3}\cell{Real}\cell{Output is current phase number}\cell\row
\intbl{\b N+4}\cell{Bit}\cell{Output indicates insert step done}\cell\row
\intbl{\b N+5}\cell{Bit}\cell{Hold state: 0 - run, 1 - hold}\cell\row\par
#135
\intbl{\b S1}\cell{Block number of next sequence manager block}\cell\row
\intbl{\b S2}\cell{Manager type - request number (0=FIFO 1=lowest)}\cell\row
\intbl{\b S3}\cell{Hold/reset (1=hold)}\cell\row
\intbl{\b S4}\cell{Complete trigger type (0=done 1=start phase #0)}\cell\row
\intbl{\b S5}\cell{Block address trigger request 1}\cell\row
\intbl{\b S6}\cell{Block address trigger request 2}\cell\row
\intbl{\b S7}\cell{Block address trigger request 3}\cell\row
\intbl{\b S8}\cell{Block address trigger request 4}\cell\row
\intbl{\b S9}\cell{Block address trigger request 5}\cell\row
\intbl{\b S10}\cell{Block address trigger request 6}\cell\row
\intbl{\b S11}\cell{Block address trigger request 7}\cell\row
\intbl{\b S12}\cell{Block address trigger request 8}\cell\row
\intbl{\b S13}\cell{Block address trigger complete 1}\cell\row
\intbl{\b S14}\cell{Block address trigger complete 2}\cell\row
\intbl{\b S15}\cell{Block address trigger complete 3}\cell\row
\intbl{\b S16}\cell{Block address trigger complete 4}\cell\row
\intbl{\b S17}\cell{Block address trigger complete 5}\cell\row
\intbl{\b S18}\cell{Block address trigger complete 6}\cell\row
\intbl{\b S19}\cell{Block address trigger complete 7}\cell\row
\intbl{\b S20}\cell{Block address trigger complete 8}\cell\row
\intbl{\b S21}\cell{Starting phase number request 1}\cell\row
\intbl{\b S22}\cell{Starting phase number request 2}\cell\row
\intbl{\b S23}\cell{Starting phase number request 3}\cell\row
\intbl{\b S24}\cell{Starting phase number request 4}\cell\row
\intbl{\b S25}\cell{Starting phase number request 5}\cell\row
\intbl{\b S26}\cell{Starting phase number request 6}\cell\row
\intbl{\b S27}\cell{Starting phase number request 7}\cell\row
\intbl{\b S28}\cell{Starting phase number request 8}\cell\row
\intbl{\b S29}\cell{Spare 1}\cell\row
\intbl{\b S30}\cell{Spare 2}\cell\row
\intbl{\b S31}\cell{Spare 3}\cell\row
\intbl{\b S32}\cell{Spare 4}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is hold/reset trigger: 0 - reset, 1 - hold}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is starting phase number}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is active request number}\cell\row\par
#136
\intbl{\b S1}\cell{Start}\cell\row
\intbl{\b S2}\cell{Stop}\cell\row
\intbl{\b S3}\cell{Block address interlock 1}\cell\row
\intbl{\b S4}\cell{Block address interlock 2}\cell\row
\intbl{\b S5}\cell{Block address interlock 3}\cell\row
\intbl{\b S6}\cell{Block address interlock 4}\cell\row
\intbl{\b S7}\cell{Feedback 1}\cell\row
\intbl{\b S8}\cell{Feedback 2}\cell\row
\intbl{\b S9}\cell{Block address start permissive 1}\cell\row
\intbl{\b S10}\cell{Block address start permissive 2}\cell\row
\intbl{\b S11}\cell{Startup feedback wait time (seconds)}\cell\row
\intbl{\b S12}\cell{Pulse-on time (seconds)}\cell\row
\intbl{\b S13}\cell{Pulse-off time (seconds)}\cell\row
\intbl{\b S14}\cell{Display type}\cell\row
\intbl{\b S15}\cell{Spare 1}\cell\row
\intbl{\b S16}\cell{Status control}\cell\row
\intbl{\b S17}\cell{Shutdown feedback wait time (seconds)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Run state: 1 - running, 0 - stopped}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Output is on pulse}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Output is off pulse}\cell\row
\intbl{\b N+3}\cell{Real}\cell{Control output status: 0.0 - good, 1.0 - alarm, 2.0 - waiting for feedback}\cell\row\par
#137
\intbl{\b S1}\cell{Dummy specification not used}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is set by BOUT command (C or BASIC program)}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is set by BOUT command (C or BASIC program)}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is set by BOUT command (C or BASIC program)}\cell\row
\intbl{\b N+3}\cell{Real}\cell{Output is set by BOUT command (C or BASIC program)}\cell\row\par
#138
\intbl{\b S1}\cell{Dummy specification not used}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is set by BOUT command (C or BASIC program)}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Output is set by BOUT command (C or BASIC program)}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Output is set by BOUT command (C or BASIC program)}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Output is set by BOUT command (C or BASIC program)}\cell\row\par
#139
\intbl{\b S1}\cell{Station (FC 80)}\cell\row
\intbl{\b S2}\cell{Setpoint raise}\cell\row
\intbl{\b S3}\cell{Setpoint lower}\cell\row
\intbl{\b S4}\cell{Control output raise}\cell\row
\intbl{\b S5}\cell{Control output lower}\cell\row
\intbl{\b S6}\cell{Auto/manual permissive}\cell\row
\intbl{\b S7}\cell{Auto/manual transfer}\cell\row
\intbl{\b S8}\cell{Manual bypass request}\cell\row
\intbl{\b S9}\cell{Bypass control output}\cell\row
\intbl{\b S10}\cell{Check input quality (1=enabled 0=disabled)}\cell\row
\intbl{\b S11}\cell{Setpoint ramp rate (units/sec)}\cell\row
\intbl{\b S12}\cell{Control output ramp rate (units/sec)}\cell\row
\intbl{\b S13}\cell{Bad quality option - bypass control output}\cell\row
\intbl{\b S14}\cell{Spare real input}\cell\row
\intbl{\b S15}\cell{Bypass control output maximum rate change (units/sec)}\cell\row
\intbl{\b S16}\cell{Spare real input}\cell\row
\intbl{\b S17}\cell{Spare boolean input}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output requests auto bypass}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Reserved}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Reserved}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Reserved}\cell\row
\intbl{\b N+4}\cell{Bit}\cell{Reserved}\cell\row\par
#140
\intbl{\b S1}\cell{Block address to be restored}\cell\row
\intbl{\b S2}\cell{Save flag}\cell\row
\intbl{\b S3}\cell{Permissive save flag}\cell\row
\intbl{\b S4}\cell{Restore condition}\cell\row
\intbl{\b S5}\cell{Slave address of digital input}\cell\row
\intbl{\b S6}\cell{Point number of digital input}\cell\row
\intbl{\b S7}\cell{Spare}\cell\row
\intbl{\b S8}\cell{Spare}\cell\row
\intbl{\b S9}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{No output}\cell\row\par
#141
\intbl{\b S1}\cell{Sequence slave (0=end)}\cell\row
\intbl{\b S2}\cell{Step jump trigger}\cell\row
\intbl{\b S3}\cell{Step jump number}\cell\row
\intbl{\b S4}\cell{Default mask}\cell\row
\intbl{\b S5}\cell{Mask step 1}\cell\row
\intbl{\b S6}\cell{Mask step 2}\cell\row
\intbl{\b S7}\cell{Mask step 3}\cell\row
\intbl{\b S8}\cell{Mask step 4}\cell\row
\intbl{\b S9}\cell{Mask step 5}\cell\row
\intbl{\b S10}\cell{Mask step 6}\cell\row
\intbl{\b S11}\cell{Mask step 7}\cell\row
\intbl{\b S12}\cell{Mask step 8}\cell\row
\intbl{\b S13}\cell{Mask step 9}\cell\row
\intbl{\b S14}\cell{Mask step 10}\cell\row
\intbl{\b S15}\cell{Mask step 11}\cell\row
\intbl{\b S16}\cell{Mask step 12}\cell\row
\intbl{\b S17}\cell{Mask step 13}\cell\row
\intbl{\b S18}\cell{Mask step 14}\cell\row
\intbl{\b S19}\cell{Mask step 15}\cell\row
\intbl{\b S20}\cell{Mask step 16}\cell\row
\intbl{\b S21}\cell{Mask step 17}\cell\row
\intbl{\b S22}\cell{Mask step 18}\cell\row
\intbl{\b S23}\cell{Mask step 19}\cell\row
\intbl{\b S24}\cell{Mask step 20}\cell\row
\intbl{\b S25}\cell{Mask step 21}\cell\row
\intbl{\b S26}\cell{Mask step 22}\cell\row
\intbl{\b S27}\cell{Mask step 23}\cell\row
\intbl{\b S28}\cell{Mask step 24}\cell\row
\intbl{\b S29}\cell{Mask step 25}\cell\row
\intbl{\b S30}\cell{Mask step 26}\cell\row
\intbl{\b S31}\cell{Mask step 27}\cell\row
\intbl{\b S32}\cell{Mask step 28}\cell\row
\intbl{\b S33}\cell{Mask step 29}\cell\row
\intbl{\b S34}\cell{Mask step 30}\cell\row
\intbl{\b S35}\cell{Mask step 31}\cell\row
\intbl{\b S36}\cell{Mask step 32}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is ones digit of mask}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Output is tens digit of mask}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Output is hundreds digit of mask}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Output is thousands digit of mask}\cell\row
\intbl{\b N+4}\cell{Real}\cell{Output is current step number}\cell\row\par
#142
\intbl{\b S1}\cell{Next sequence slave (0=end)}\cell\row
\intbl{\b S2}\cell{Mask step N + 1}\cell\row
\intbl{\b S3}\cell{Mask step N + 2}\cell\row
\intbl{\b S4}\cell{Mask step N + 3}\cell\row
\intbl{\b S5}\cell{Mask step N + 4}\cell\row
\intbl{\b S6}\cell{Mask step N + 5}\cell\row
\intbl{\b S7}\cell{Mask step N + 6}\cell\row
\intbl{\b S8}\cell{Mask step N + 7}\cell\row
\intbl{\b S9}\cell{Mask step N + 8}\cell\row
\intbl{\b S10}\cell{Mask step N + 9}\cell\row
\intbl{\b S11}\cell{Mask step N + 10}\cell\row
\intbl{\b S12}\cell{Mask step N + 11}\cell\row
\intbl{\b S13}\cell{Mask step N + 12}\cell\row
\intbl{\b S14}\cell{Mask step N + 13}\cell\row
\intbl{\b S15}\cell{Mask step N + 14}\cell\row
\intbl{\b S16}\cell{Mask step N + 15}\cell\row
\intbl{\b S17}\cell{Mask step N + 16}\cell\row
\intbl{\b S18}\cell{Mask step N + 17}\cell\row
\intbl{\b S19}\cell{Mask step N + 18}\cell\row
\intbl{\b S20}\cell{Mask step N + 19}\cell\row
\intbl{\b S21}\cell{Mask step N + 20}\cell\row
\intbl{\b S22}\cell{Mask step N + 21}\cell\row
\intbl{\b S23}\cell{Mask step N + 22}\cell\row
\intbl{\b S24}\cell{Mask step N + 23}\cell\row
\intbl{\b S25}\cell{Mask step N + 24}\cell\row
\intbl{\b S26}\cell{Mask step N + 25}\cell\row
\intbl{\b S27}\cell{Mask step N + 26}\cell\row
\intbl{\b S28}\cell{Mask step N + 27}\cell\row
\intbl{\b S29}\cell{Mask step N + 28}\cell\row
\intbl{\b S30}\cell{Mask step N + 29}\cell\row
\intbl{\b S31}\cell{Mask step N + 30}\cell\row
\intbl{\b S32}\cell{Mask step N + 31}\cell\row
\intbl{\b S33}\cell{Mask step N + 32}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{No output}\cell\row\par
#143
\intbl{\b S1}\cell{Program operating mode: (0=normal, 1=inhibited, 2=debug)}\cell\row
\intbl{\b S2}\cell{Inhibit execution flag}\cell\row
\intbl{\b or}\cell{(see manual)}\cell\row
\intbl{\b S1}\cell{Inhibit execution flag #1}\cell\row
\intbl{\b S2}\cell{Inhibit execution flag #2}\cell\row
\intbl{\b S3}\cell{Program readable parameter}\cell\row
\intbl{\b S4}\cell{Program readable parameter}\cell\row
\intbl{\b S5}\cell{Program readable parameter}\cell\row
\intbl{\b S6}\cell{Program readable parameter}\cell\row
\intbl{\b S7}\cell{Program readable parameter}\cell\row
\intbl{\b S8}\cell{Program readable parameter}\cell\row
\intbl{\b S9}\cell{Spare 1}\cell\row
\intbl{\b S10}\cell{Spare 2}\cell\row
\intbl{\b S11}\cell{Spare 3}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is value set by C program with putargs function}\cell\row\par
#144
\intbl{\b S1}\cell{C RAM allocation (1K byte increments)}\cell\row
\intbl{\b S2}\cell{C NVRAM allocation (1K byte increments)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Reserved}\cell\row\par
#145
\intbl{\b S1}\cell{Slave address}\cell\row
\intbl{\b S2}\cell{Spare}\cell\row
\intbl{\b S3}\cell{Spare}\cell\row
\intbl{\b S4}\cell{Spare}\cell\row
\intbl{\b S5}\cell{Gain}\cell\row
\intbl{\b S6}\cell{High alarm value}\cell\row
\intbl{\b S7}\cell{Low alarm value}\cell\row
\intbl{\b S8}\cell{Absolute alarm deadband}\cell\row
\intbl{\b S9}\cell{Rate of change alarm signal}\cell\row
\intbl{\b S10}\cell{Spare 2}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is frequency times gain with alarm}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{High alarm: 0 - good, 1 - alarm}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Low alarm: 0 - good, 1 - alarm}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Slave communication status: 0 - good, 1 - bad}\cell\row\par
#146
\intbl{\b S1}\cell{Remote I/O definition (0=end)}\cell\row
\intbl{\b S2}\cell{Expander bus address primary RMP}\cell\row
\intbl{\b S3}\cell{Expander bus address secondary RMP}\cell\row
\intbl{\b S4}\cell{Spare}\cell\row
\intbl{\b S5}\cell{Block address of control or indicator station}\cell\row
\intbl{\b S6}\cell{Block address of control or indicator station}\cell\row
\intbl{\b S7}\cell{Block address of control or indicator station}\cell\row
\intbl{\b S8}\cell{Block address of control or indicator station}\cell\row
\intbl{\b S9}\cell{Block address of control or indicator station}\cell\row
\intbl{\b S10}\cell{Block address of control or indicator station}\cell\row
\intbl{\b S11}\cell{Block address of control or indicator station}\cell\row
\intbl{\b S12}\cell{Block address of control or indicator station}\cell\row
\intbl{\b S13}\cell{Block address of control or indicator station}\cell\row
\intbl{\b S14}\cell{Block address of control or indicator station}\cell\row
\intbl{\b S15}\cell{Block address of control or indicator station}\cell\row
\intbl{\b S16}\cell{Block address of control or indicator station}\cell\row
\intbl{\b S17}\cell{Spare boolean input}\cell\row
\intbl{\b S18}\cell{Spare boolean input}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Primary RMP status: 0 - good, 1 - bad}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Secondary RMP status: 0 - good, 1 - bad}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is cycle time of RMP}\cell\row\par
#147
\intbl{\b S1}\cell{Next remote I/O definition (0=end)}\cell\row
\intbl{\b S2}\cell{Remote slave processor serial link communication address}\cell\row
\intbl{\b S3}\cell{Spare}\cell\row
\intbl{\b S4}\cell{Spare}\cell\row
\intbl{\b S5}\cell{I/O block}\cell\row
\intbl{\b S6}\cell{I/O block}\cell\row
\intbl{\b S7}\cell{I/O block}\cell\row
\intbl{\b S8}\cell{I/O block}\cell\row
\intbl{\b S9}\cell{I/O block}\cell\row
\intbl{\b S10}\cell{I/O block}\cell\row
\intbl{\b S11}\cell{I/O block}\cell\row
\intbl{\b S12}\cell{I/O block}\cell\row
\intbl{\b S13}\cell{I/O block}\cell\row
\intbl{\b S14}\cell{I/O block}\cell\row
\intbl{\b S15}\cell{I/O block}\cell\row
\intbl{\b S16}\cell{I/O block}\cell\row
\intbl{\b S17}\cell{I/O block}\cell\row
\intbl{\b S18}\cell{I/O block}\cell\row
\intbl{\b S19}\cell{I/O block}\cell\row
\intbl{\b S20}\cell{I/O block}\cell\row
\intbl{\b S21}\cell{I/O block}\cell\row
\intbl{\b S22}\cell{I/O block}\cell\row
\intbl{\b S23}\cell{I/O block}\cell\row
\intbl{\b S24}\cell{I/O block}\cell\row
\intbl{\b S25}\cell{I/O block}\cell\row
\intbl{\b S26}\cell{I/O block}\cell\row
\intbl{\b S27}\cell{I/O block}\cell\row
\intbl{\b S28}\cell{I/O block}\cell\row
\intbl{\b S29}\cell{I/O block}\cell\row
\intbl{\b S30}\cell{I/O block}\cell\row
\intbl{\b S31}\cell{I/O block}\cell\row
\intbl{\b S32}\cell{I/O block}\cell\row
\intbl{\b S33}\cell{I/O block}\cell\row
\intbl{\b S34}\cell{I/O block}\cell\row
\intbl{\b S35}\cell{I/O block}\cell\row
\intbl{\b S36}\cell{I/O block}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Remote slave processor status: 0 - good, 1 - bad}\cell\row\par
#148
\intbl{\b S1}\cell{Recipe number}\cell\row
\intbl{\b S2}\cell{Phase number}\cell\row
\intbl{\b S3}\cell{Run/hold pushbutton}\cell\row
\intbl{\b S4}\cell{Operator acknowledge pushbutton}\cell\row
\intbl{\b S5}\cell{Emergency stop}\cell\row
\intbl{\b S6}\cell{Spare boolean input}\cell\row
\intbl{\b S7}\cell{Spare boolean input}\cell\row
\intbl{\b S8}\cell{Sequence ID number}\cell\row
\intbl{\b S9}\cell{Program ID number}\cell\row
\intbl{\b S10}\cell{Debug mode (1=advance 2=hold 3=abort)}\cell\row
\intbl{\b S11}\cell{Program space allocation (1K byte increments)}\cell\row
\intbl{\b S12}\cell{Data space allocation (1 byte increments)}\cell\row
\intbl{\b S13}\cell{Spare}\cell\row
\intbl{\b S14}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is current recipe ID number}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is current phase number}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Run status: 0 - hold, 1 - run}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Fault logic active: 0 - no, 1 - yes}\cell\row
\intbl{\b N+4}\cell{Bit}\cell{Hold logic active: 0 - no, 1 - yes}\cell\row
\intbl{\b N+5}\cell{Bit}\cell{Batch complete: 0 - no, 1 - yes}\cell\row
\intbl{\b N+6}\cell{Bit}\cell{Reset operator acknowledge: 0 - no, 1 - yes}\cell\row
\intbl{\b N+7}\cell{Real}\cell{Output is fault code}\cell\row
\intbl{\b N+8}\cell{Real}\cell{Output is current statement number}\cell\row\par
#149
\intbl{\b S1}\cell{Slave address}\cell\row
\intbl{\b S2}\cell{Block address of next analog output/slave}\cell\row
\intbl{\b S3}\cell{Continue on slave error}\cell\row
\intbl{\b S4}\cell{Output N}\cell\row
\intbl{\b S5}\cell{Output N + 1}\cell\row
\intbl{\b S6}\cell{Output N + 2}\cell\row
\intbl{\b S7}\cell{Output N + 3}\cell\row
\intbl{\b S8}\cell{Output N + 4}\cell\row
\intbl{\b S9}\cell{Output N + 5}\cell\row
\intbl{\b S10}\cell{Output N + 6}\cell\row
\intbl{\b S11}\cell{Default state, output N}\cell\row
\intbl{\b S12}\cell{Default state, output N + 1}\cell\row
\intbl{\b S13}\cell{Default state, output N + 2}\cell\row
\intbl{\b S14}\cell{Default state, output N + 3}\cell\row
\intbl{\b S15}\cell{Default state, output N + 4}\cell\row
\intbl{\b S16}\cell{Default state, output N + 5}\cell\row
\intbl{\b S17}\cell{Default state, output N + 6}\cell\row
\intbl{\b S18}\cell{Engineering units zero for output N}\cell\row
\intbl{\b S19}\cell{Engineering units span for output N}\cell\row
\intbl{\b S20}\cell{Engineering units zero for output N + 1}\cell\row
\intbl{\b S21}\cell{Engineering units span for output N + 1}\cell\row
\intbl{\b S22}\cell{Engineering units zero for output N + 2}\cell\row
\intbl{\b S23}\cell{Engineering units span for output N + 2}\cell\row
\intbl{\b S24}\cell{Engineering units zero for output N + 3}\cell\row
\intbl{\b S25}\cell{Engineering units span for output N + 3}\cell\row
\intbl{\b S26}\cell{Engineering units zero for output N + 4}\cell\row
\intbl{\b S27}\cell{Engineering units span for output N + 4}\cell\row
\intbl{\b S28}\cell{Engineering units zero for output N + 5}\cell\row
\intbl{\b S29}\cell{Engineering units span for output N + 5}\cell\row
\intbl{\b S30}\cell{Engineering units zero for output N + 6}\cell\row
\intbl{\b S31}\cell{Engineering units span for output N + 6}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is value of analog output 1}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is value of analog output 2}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is value of analog output 3}\cell\row
\intbl{\b N+3}\cell{Real}\cell{Output is value of analog output 4}\cell\row
\intbl{\b N+4}\cell{Real}\cell{Output is value of analog output 5}\cell\row
\intbl{\b N+5}\cell{Real}\cell{Output is value of analog output 6}\cell\row
\intbl{\b N+6}\cell{Real}\cell{Output is value of analog output 7}\cell\row
\intbl{\b N+7}\cell{Real}\cell{Slave status: 0 - good, 1 - bad}\cell\row\par
#150
\intbl{\b S1}\cell{Slave address}\cell\row
\intbl{\b S2}\cell{Percent position demand}\cell\row
\intbl{\b S3}\cell{Calibrate select}\cell\row
\intbl{\b S4}\cell{Resume/hold}\cell\row
\intbl{\b S5}\cell{Null check select}\cell\row
\intbl{\b S6}\cell{Calibration stroke time selection}\cell\row
\intbl{\b S7}\cell{Calibration cycles count}\cell\row
\intbl{\b S8}\cell{LVDT differential voltage at 0% actuator position}\cell\row
\intbl{\b S9}\cell{LVDT differential voltage at 100% actuator position}\cell\row
\intbl{\b S10}\cell{Spare 1}\cell\row
\intbl{\b S11}\cell{Spare 2}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is actuator position with quality}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Differential voltage at null point: 0 - no, 1 - yes}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Actuator positioning status: 0 - good, 1 - bad}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{A/D or D/A status: 0 - good, 1 - bad}\cell\row
\intbl{\b N+4}\cell{Bit}\cell{LVDT primary status: 0 - good, 1 - bad}\cell\row
\intbl{\b N+5}\cell{Bit}\cell{LVDT secondary status: 0 - good, 1 - bad}\cell\row
\intbl{\b N+6}\cell{Bit}\cell{Output 1 status: 0 - good, 1 - bad}\cell\row
\intbl{\b N+7}\cell{Bit}\cell{Output 2 status: 0 - good, 1 - bad}\cell\row
\intbl{\b N+8}\cell{Bit}\cell{Slave mode: 0 - normal, 1 - E-STOP manual}\cell\row
\intbl{\b N+9}\cell{Bit}\cell{Calibrate status: 0 - in progress, 1 - complete}\cell\row
\intbl{\b N+10}\cell{Bit}\cell{Slave hardware status: 0 - good, 1 - bad}\cell\row
\intbl{\b N+11}\cell{Bit}\cell{Slave communication and watchdog timer status: 0 - good, 1 - bad}\cell\row\par
#151
\intbl{\b S1}\cell{Message number}\cell\row
\intbl{\b S2}\cell{Color select}\cell\row
\intbl{\b S3}\cell{Blink select}\cell\row
\intbl{\b S4}\cell{Control status}\cell\row
\intbl{\b S5}\cell{Good control status message number}\cell\row
\intbl{\b S6}\cell{Good control status color select}\cell\row
\intbl{\b S7}\cell{Good control status blink select}\cell\row
\intbl{\b S8}\cell{Bad control status message number}\cell\row
\intbl{\b S9}\cell{Bad control status color select}\cell\row
\intbl{\b S10}\cell{Bad control status blink select}\cell\row
\intbl{\b S11}\cell{Wait control status message number}\cell\row
\intbl{\b S12}\cell{Wait control status color select}\cell\row
\intbl{\b S13}\cell{Wait control status blink select}\cell\row
\intbl{\b S14}\cell{Spare integer input}\cell\row
\intbl{\b S15}\cell{Spare 2}\cell\row
\intbl{\b S16}\cell{Spare 3}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is message number}\cell\row\par   
#152
\intbl{\b S1}\cell{Process variable}\cell\row
\intbl{\b S2}\cell{Control output}\cell\row
\intbl{\b S3}\cell{Reset trigger (0 to 1)}\cell\row
\intbl{\b S4}\cell{Estimator sample time (sec)}\cell\row
\intbl{\b S5}\cell{Process deadtime (sec)}\cell\row
\intbl{\b S6}\cell{Expected process noise level (peak to peak)}\cell\row
\intbl{\b S7}\cell{Spare real parameter}\cell\row
\intbl{\b S8}\cell{Spare boolean input}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is parameter a}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is parameter b}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is parameter c}\cell\row
\intbl{\b N+3}\cell{Real}\cell{Output is difference between actual and calculated data}\cell\row
\intbl{\b N+4}\cell{Bit}\cell{Model quality: 0 - estimator locked on, 1 - new estimation in progress}\cell\row\par
#153
\intbl{\b S1}\cell{Associated model parameter estimator}\cell\row
\intbl{\b S2}\cell{Associated inferential smith controller (ISC)}\cell\row
\intbl{\b S3}\cell{Process deadtime}\cell\row
\intbl{\b S4}\cell{Hold signal}\cell\row
\intbl{\b S5}\cell{Process gain value minimum}\cell\row
\intbl{\b S6}\cell{Process gain value maximum}\cell\row
\intbl{\b S7}\cell{Minimum process lag time constant}\cell\row
\intbl{\b S8}\cell{Maximum process lag time constant}\cell\row
\intbl{\b S9}\cell{Adapt option}\cell\row
\intbl{\b S10}\cell{Initialization trigger}\cell\row
\intbl{\b S11}\cell{Maximum control output change for initialization}\cell\row
\intbl{\b S12}\cell{Spare real parameter}\cell\row
\intbl{\b S13}\cell{Spare boolean input}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is estimated process gain}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is estimated process time constant}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is adjusted process deadtime}\cell\row
\intbl{\b N+3}\cell{Real}\cell{Output is estimated process operating point}\cell\row
\intbl{\b N+4}\cell{Real}\cell{Initialization status: 0 - complete, 1 - failed or aborted, 2 - in progress}\cell\row
\intbl{\b N+5}\cell{Bit}\cell{Output is pulse initiated after completion of the automated initialization routine}\cell\row\par
#154
\intbl{\b S1}\cell{Index variable}\cell\row
\intbl{\b S2}\cell{Fixed gain schedule}\cell\row
\intbl{\b S3}\cell{Scheduled parameter}\cell\row
\intbl{\b S4}\cell{Reset trigger}\cell\row
\intbl{\b S5}\cell{Block number containing specification to be adapted}\cell\row
\intbl{\b S6}\cell{Specification to be adapted}\cell\row
\intbl{\b S7}\cell{Minimum index value}\cell\row
\intbl{\b S8}\cell{Maximum index value}\cell\row
\intbl{\b S9}\cell{Spare}\cell\row
\intbl{\b S10}\cell{Coefficient update hold}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is scheduled tuning parameter}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is correction coefficient A}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is correction coefficient B}\cell\row\par
#155
\intbl{\b S1}\cell{Dependent variable}\cell\row
\intbl{\b S2}\cell{Independent variable X1}\cell\row
\intbl{\b S3}\cell{Independent variable X2}\cell\row
\intbl{\b S4}\cell{Independent variable X3}\cell\row
\intbl{\b S5}\cell{Independent variable X4}\cell\row
\intbl{\b S6}\cell{Number of independent variables to use}\cell\row
\intbl{\b S7}\cell{Number of data sets to buffer}\cell\row
\intbl{\b S8}\cell{Minimum number of good sets required}\cell\row
\intbl{\b S9}\cell{Time/trigger mode flag 0-trigger 1-time}\cell\row
\intbl{\b S10}\cell{Time between calculations (minutes)}\cell\row
\intbl{\b S11}\cell{External trigger}\cell\row
\intbl{\b S12}\cell{Data storage mode flag 0-sequential 1-bins}\cell\row
\intbl{\b S13}\cell{High range of independent variable 1}\cell\row
\intbl{\b S14}\cell{Low range of independent variable 1}\cell\row
\intbl{\b S15}\cell{Edit mode switch 0-calculate 1-edit}\cell\row
\intbl{\b S16}\cell{Set to edit value}\cell\row
\intbl{\b S17}\cell{Set quality toggle flag}\cell\row
\intbl{\b S18}\cell{Reset flag 1-reset}\cell\row
\intbl{\b S19}\cell{Initial default for parameter 1}\cell\row
\intbl{\b S20}\cell{Initial default for parameter 2}\cell\row
\intbl{\b S21}\cell{Initial default for parameter 3}\cell\row
\intbl{\b S22}\cell{Initial default for parameter 4}\cell\row
\intbl{\b S23}\cell{Desired goodness of fit}\cell\row
\intbl{\b S24}\cell{Default update period (hours)}\cell\row
\intbl{\b S25}\cell{Spare}\cell\row
\intbl{\b S26}\cell{Spare}\cell\row
\intbl{\b S27}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Calculate mode outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is parameter 1}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is parameter 2}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is parameter 3}\cell\row
\intbl{\b N+3}\cell{Real}\cell{Output is parameter 4}\cell\row
\intbl{\b N+4}\cell{Real}\cell{Output is goodness of fit}\cell\row
\intbl{\b N+5}\cell{Real}\cell{Output is maximum model mismatch}\cell\row
\intbl{\b N+6}\cell{Real}\cell{Output is number of row number causing maximum model mismatch}\cell\row
\intbl{\b N+7}\cell{Real}\cell{Output is number of rows with good quality}\cell\row
\intbl{\b N+8}\cell{Real}\cell{Output is time of last computation}\cell\row
\intbl{\b N+9}\cell{Real}\cell{State of outputs - 0=computed, 1=default}\cell\row
\sb120\li120\sa120{\fs28\b Edit Mode Outputs}\par\pard
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is parameter 1}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is parameter 2}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is parameter 3}\cell\row
\intbl{\b N+3}\cell{Real}\cell{Output is parameter 4}\cell\row
\intbl{\b N+4}\cell{Real}\cell{Output is dependent variable, (y)}\cell\row
\intbl{\b N+5}\cell{Real}\cell{Output is independent variable 1, (x1)}\cell\row
\intbl{\b N+6}\cell{Real}\cell{Output is independent variable 2, (x2)}\cell\row
\intbl{\b N+7}\cell{Real}\cell{Output is independent variable 3, (x3)}\cell\row\par
\intbl{\b N+8}\cell{Real}\cell{Output is independent variable 4, (x4)}\cell\row\par
\intbl{\b N+9}\cell{Real}\cell{Quality of data point - 0=bad, excluded; 1=good, included}\cell\row
#156
\intbl{\b S1}\cell{Process value}\cell\row
\intbl{\b S2}\cell{Setpoint}\cell\row
\intbl{\b S3}\cell{Track reference signal}\cell\row
\intbl{\b S4}\cell{Track/release flag}\cell\row
\intbl{\b S5}\cell{PID external reset}\cell\row
\intbl{\b S6}\cell{Feed forward}\cell\row
\intbl{\b S7}\cell{Spare real input}\cell\row
\intbl{\b S8}\cell{Spare boolean input}\cell\row
\intbl{\b S9}\cell{Prevent increase}\cell\row
\intbl{\b S10}\cell{Prevent decrease}\cell\row
\intbl{\b S11}\cell{(K) gain multiplier}\cell\row
\intbl{\b S12}\cell{(KP) proportional constant}\cell\row
\intbl{\b S13}\cell{(KI) integral or manual reset time constant (minute)}\cell\row
\intbl{\b S14}\cell{(KD) derivative constant (minute)}\cell\row
\intbl{\b S15}\cell{(KA) derivative lag constant}\cell\row
\intbl{\b S16}\cell{High output limit}\cell\row
\intbl{\b S17}\cell{Low output limit}\cell\row
\intbl{\b S18}\cell{Algorithm type}\cell\row
\intbl{\b S19}\cell{Integral limit type}\cell\row
\intbl{\b S20}\cell{Setpoint modifier}\cell\row
\intbl{\b S21}\cell{Direction switch}\cell\row
\intbl{\b S22}\cell{Spare real parameter}\cell\row
\intbl{\b S23}\cell{Spare integer parameter}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is control output with feed forward}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Block increase: 0 - permit increase, 1 - inhibit increase}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Block decrease flag: 0 - permit decrease, 1 - inhibit decrease}\cell\row\par
#157
\intbl{\b S1}\cell{Process value}\cell\row
\intbl{\b S2}\cell{Setpoint}\cell\row
\intbl{\b S3}\cell{Track value}\cell\row
\intbl{\b S4}\cell{Feed forward}\cell\row
\intbl{\b S5}\cell{Release / track flag}\cell\row
\intbl{\b S6}\cell{Execution mode 0-trigger 1-time}\cell\row
\intbl{\b S7}\cell{External trigger}\cell\row
\intbl{\b S8}\cell{Time between runs (sec)}\cell\row
\intbl{\b S9}\cell{High output limit}\cell\row
\intbl{\b S10}\cell{Low output limit}\cell\row
\intbl{\b S11}\cell{Coefficient A0}\cell\row
\intbl{\b S12}\cell{Coefficient A1}\cell\row
\intbl{\b S13}\cell{Coefficient A2}\cell\row
\intbl{\b S14}\cell{Coefficient A3}\cell\row
\intbl{\b S15}\cell{Coefficient A4}\cell\row
\intbl{\b S16}\cell{Coefficient B0}\cell\row
\intbl{\b S17}\cell{Coefficient B1}\cell\row
\intbl{\b S18}\cell{Coefficient B2}\cell\row
\intbl{\b S19}\cell{Coefficient B3}\cell\row
\intbl{\b S20}\cell{Coefficient B4}\cell\row
\intbl{\b S21}\cell{Numerator dead time (number of intervals)}\cell\row
\intbl{\b S22}\cell{Denominator dead time (number of intervals)}\cell\row
\intbl{\b S23}\cell{Spare}\cell\row
\intbl{\b S24}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is function value}\cell\row\par
#158
\intbl{\b S1}\cell{Input type}\cell\row
\intbl{\b S2}\cell{Engineering units}\cell\row
\intbl{\b S3}\cell{Engineering units ID}\cell\row
\intbl{\b S4}\cell{Engineering units zero of input}\cell\row
\intbl{\b S5}\cell{Engineering units span of input}\cell\row
\intbl{\b S6}\cell{Significant change (percent of span)}\cell\row
\intbl{\b S7}\cell{High alarm value}\cell\row
\intbl{\b S8}\cell{Low alarm value}\cell\row
\intbl{\b S9}\cell{Leadwire resistance}\cell\row
\intbl{\b S10}\cell{Block number of polynomial block}\cell\row
\intbl{\b S11}\cell{Block number of cold junction input block.}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is input value with quality}\cell\row\par
#159
\intbl{\b S1}\cell{Coefficient A mantissa}\cell\row
\intbl{\b S2}\cell{Coefficient A exponent}\cell\row
\intbl{\b S3}\cell{Coefficient B mantissa}\cell\row
\intbl{\b S4}\cell{Coefficient B exponent}\cell\row
\intbl{\b S5}\cell{Coefficient C mantissa}\cell\row
\intbl{\b S6}\cell{Coefficient C exponent}\cell\row
\intbl{\b S7}\cell{Coefficient D mantissa}\cell\row
\intbl{\b S8}\cell{Coefficient D exponent}\cell\row
\intbl{\b S9}\cell{Coefficient E mantissa}\cell\row
\intbl{\b S10}\cell{Coefficient E exponent}\cell\row
\intbl{\b S11}\cell{Coefficient F mantissa}\cell\row
\intbl{\b S12}\cell{Coefficient F exponent}\cell\row
\intbl{\b S13}\cell{Pre-scale exponent}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{No output}\cell\row\par
#160
\intbl{\b S1}\cell{Process value}\cell\row
\intbl{\b S2}\cell{Setpoint}\cell\row
\intbl{\b S3}\cell{Track reference value}\cell\row
\intbl{\b S4}\cell{Track switch signal (0=track 1=release)}\cell\row
\intbl{\b S5}\cell{External reference value}\cell\row
\intbl{\b S6}\cell{External reference switch (0=normal 1=use external reference)}\cell\row
\intbl{\b S7}\cell{Process gain value}\cell\row
\intbl{\b S8}\cell{Process deadtime (seconds)}\cell\row
\intbl{\b S9}\cell{Process lag time constant (seconds)}\cell\row
\intbl{\b S10}\cell{Process tuning time constant (seconds)}\cell\row
\intbl{\b S11}\cell{High output limit}\cell\row
\intbl{\b S12}\cell{Low output limit}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is control output}\cell\row\par
#161
\intbl{\b S1}\cell{Starting block address of previous sequence generator}\cell\row
\intbl{\b S2}\cell{Step trigger (0 to 1)}\cell\row
\intbl{\b S3}\cell{Step hold (0-release 1-hold)}\cell\row
\intbl{\b S4}\cell{Timer hold(0-release 1-hold)}\cell\row
\intbl{\b S5}\cell{Reset trigger (0 to 1)}\cell\row
\intbl{\b S6}\cell{Jump trigger (0 to 1)}\cell\row
\intbl{\b S7}\cell{Step jump number}\cell\row
\intbl{\b S8}\cell{Output disable flag}\cell\row
\intbl{\b S9}\cell{Disabled output state}\cell\row
\intbl{\b S10}\cell{Output mask step number 1}\cell\row
\intbl{\b S11}\cell{Time in seconds step number 1}\cell\row
\intbl{\b S12}\cell{Output mask step number 2}\cell\row
\intbl{\b S13}\cell{Time in seconds step number 2}\cell\row
\intbl{\b S14}\cell{Output mask step number 3}\cell\row
\intbl{\b S15}\cell{Time in seconds step number 3}\cell\row
\intbl{\b S16}\cell{Output mask step number 4}\cell\row
\intbl{\b S17}\cell{Time in seconds step number 4}\cell\row
\intbl{\b S18}\cell{Output mask step number 5}\cell\row
\intbl{\b S19}\cell{Time in seconds step number 5}\cell\row
\intbl{\b S20}\cell{Output mask step number 6}\cell\row
\intbl{\b S21}\cell{Time in seconds step number 6}\cell\row
\intbl{\b S22}\cell{Output mask step number 7}\cell\row
\intbl{\b S23}\cell{Time in seconds step number 7}\cell\row
\intbl{\b S24}\cell{Output mask step number 8}\cell\row
\intbl{\b S25}\cell{Time in seconds step number 8}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output 1}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Output 2}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Output 3}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Output 4}\cell\row
\intbl{\b N+4}\cell{Bit}\cell{Output 5}\cell\row
\intbl{\b N+5}\cell{Bit}\cell{Output 6}\cell\row
\intbl{\b N+6}\cell{Bit}\cell{Output 7}\cell\row
\intbl{\b N+7}\cell{Bit}\cell{Output 8}\cell\row
\intbl{\b N+8}\cell{Real}\cell{Output is current step number}\cell\row
\intbl{\b N+9}\cell{Real}\cell{Output is time remaining in current step}\cell\row
\intbl{\b N+10}\cell{Bit}\cell{Output indicates advance to next step}\cell\row\par
#162
\intbl{\b S1}\cell{Input 1}\cell\row
\intbl{\b S2}\cell{Input 2}\cell\row
\intbl{\b S3}\cell{Input 3}\cell\row
\intbl{\b S4}\cell{Input 4}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is value of input 1}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Output is value of input 2}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Output is value of input 3}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Output is value of input 4}\cell\row\par
#163
\intbl{\b S1}\cell{Input 1}\cell\row
\intbl{\b S2}\cell{Input 2}\cell\row
\intbl{\b S3}\cell{Input 3}\cell\row
\intbl{\b S4}\cell{Input 4}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is value of input 1}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is value of input 2}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is value of input 3}\cell\row
\intbl{\b N+3}\cell{Real}\cell{Output is value of input 4}\cell\row\par
#164
\intbl{\b S1}\cell{Segment priority (1=high 255=low)}\cell\row
\intbl{\b S2}\cell{Units of cycle time (0-seconds 1-minutes)}\cell\row
\intbl{\b S3}\cell{Target cycle time}\cell\row
\intbl{\b S4}\cell{Cycle time alarm limit}\cell\row
\intbl{\b S5}\cell{PID external reset option}\cell\row
\intbl{\b S6}\cell{Spare}\cell\row
\intbl{\b S7}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is segment period of previous cycle}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is execution time of the current cycle}\cell\row\par
#165
\intbl{\b S1}\cell{Input}\cell\row
\intbl{\b S2}\cell{Number of samples (N)}\cell\row
\intbl{\b S3}\cell{Interval between samples (seconds)}\cell\row
\intbl{\b S4}\cell{Track switch(1-release)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is averages of last n samples}\cell\row\par
#166
\intbl{\b S1}\cell{Process value}\cell\row
\intbl{\b S2}\cell{Time base (0=seconds 1=minutes 2=hours)}\cell\row
\intbl{\b S3}\cell{Initial value}\cell\row
\intbl{\b S4}\cell{Reset (0-reset 1-run)}\cell\row
\intbl{\b S5}\cell{High limit}\cell\row
\intbl{\b S6}\cell{Low limit}\cell\row
\intbl{\b S7}\cell{Gain}\cell\row
\intbl{\b S8}\cell{Automatic reset (0=off 1=on)}\cell\row
\intbl{\b S9}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is value of integral}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Integrator status: 0 - good, 1 - high or low limit reached}\cell\row\par
#167
\intbl{\b S1}\cell{Input X}\cell\row
\intbl{\b S2}\cell{Mantissa of H constant}\cell\row
\intbl{\b S3}\cell{Decimal exponent of H constant}\cell\row
\intbl{\b S4}\cell{Mantissa of G times X}\cell\row
\intbl{\b S5}\cell{Decimal exponent of G times X}\cell\row
\intbl{\b S6}\cell{Mantissa of F times X**2}\cell\row
\intbl{\b S7}\cell{Decimal exponent of F times X**2}\cell\row
\intbl{\b S8}\cell{Mantissa of E times X**3}\cell\row
\intbl{\b S9}\cell{Decimal exponent of E times X**3}\cell\row
\intbl{\b S10}\cell{Mantissa of D times X**4}\cell\row
\intbl{\b S11}\cell{Decimal exponent of D times X**4}\cell\row
\intbl{\b S12}\cell{Mantissa of C times X**5}\cell\row
\intbl{\b S13}\cell{Decimal exponent of C times X**5}\cell\row
\intbl{\b S14}\cell{Mantissa of B times X**6}\cell\row
\intbl{\b S15}\cell{Decimal exponent of B times X**6}\cell\row
\intbl{\b S16}\cell{Mantissa of A times X**7}\cell\row
\intbl{\b S17}\cell{Decimal exponent of A times X**7}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is value of polynomial}\cell\row\par
#168
\intbl{\b S1}\cell{Input X}\cell\row
\intbl{\b S2}\cell{Input Y}\cell\row
\intbl{\b S3}\cell{X coordinate of Z(11) [X min]}\cell\row
\intbl{\b S4}\cell{Y coordinate of Z(11) [Y max]}\cell\row
\intbl{\b S5}\cell{X coordinate of Z(55) [X max]}\cell\row
\intbl{\b S6}\cell{Y coordinate of Z(55) [Y min]}\cell\row
\intbl{\b S7}\cell{Z (11) value}\cell\row
\intbl{\b S8}\cell{Z (12) value}\cell\row
\intbl{\b S9}\cell{Z (13) value}\cell\row
\intbl{\b S10}\cell{Z (14) value}\cell\row
\intbl{\b S11}\cell{Z (15) value}\cell\row
\intbl{\b S12}\cell{Z (21) value}\cell\row
\intbl{\b S13}\cell{Z (22) value}\cell\row
\intbl{\b S14}\cell{Z (23) value}\cell\row
\intbl{\b S15}\cell{Z (24) value}\cell\row
\intbl{\b S16}\cell{Z (25) value}\cell\row
\intbl{\b S17}\cell{Z (31) value}\cell\row
\intbl{\b S18}\cell{Z (32) value}\cell\row
\intbl{\b S19}\cell{Z (33) value}\cell\row
\intbl{\b S20}\cell{Z (34) value}\cell\row
\intbl{\b S21}\cell{Z (35) value}\cell\row
\intbl{\b S22}\cell{Z (41) value}\cell\row
\intbl{\b S23}\cell{Z (42) value}\cell\row
\intbl{\b S24}\cell{Z (43) value}\cell\row
\intbl{\b S25}\cell{Z (44) value}\cell\row
\intbl{\b S26}\cell{Z (45) value}\cell\row
\intbl{\b S27}\cell{Z (51) value}\cell\row
\intbl{\b S28}\cell{Z (52) value}\cell\row
\intbl{\b S29}\cell{Z (53) value}\cell\row
\intbl{\b S30}\cell{Z (54) value}\cell\row
\intbl{\b S31}\cell{Z (55) value}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is interpolated value}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Input status: 0 - good, 1 - one or more inputs is out of range}\cell\row\par
#169
\intbl{\b S1}\cell{Matrix A row 1 column 1}\cell\row
\intbl{\b S2}\cell{Matrix A row 1 column 2}\cell\row
\intbl{\b S3}\cell{Matrix A row 1 column 3}\cell\row
\intbl{\b S4}\cell{Matrix A row 2 column 1}\cell\row
\intbl{\b S5}\cell{Matrix A row 2 column 2}\cell\row
\intbl{\b S6}\cell{Matrix A row 2 column 3}\cell\row
\intbl{\b S7}\cell{Matrix A row 3 column 1}\cell\row
\intbl{\b S8}\cell{Matrix A row 3 column 2}\cell\row
\intbl{\b S9}\cell{Matrix A row 3 column 3}\cell\row
\intbl{\b S10}\cell{Matrix B row 1 column 1}\cell\row
\intbl{\b S11}\cell{Matrix B row 1 column 2}\cell\row
\intbl{\b S12}\cell{Matrix B row 1 column 3}\cell\row
\intbl{\b S13}\cell{Matrix B row 2 column 1}\cell\row
\intbl{\b S14}\cell{Matrix B row 2 column 2}\cell\row
\intbl{\b S15}\cell{Matrix B row 2 column 3}\cell\row
\intbl{\b S16}\cell{Matrix B row 3 column 1}\cell\row
\intbl{\b S17}\cell{Matrix B row 3 column 2}\cell\row
\intbl{\b S18}\cell{Matrix B row 3 column 3}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is result R11}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is result R12}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is result R13}\cell\row
\intbl{\b N+3}\cell{Real}\cell{Output is result R21}\cell\row
\intbl{\b N+4}\cell{Real}\cell{Output is result R22}\cell\row
\intbl{\b N+5}\cell{Real}\cell{Output is result R23}\cell\row
\intbl{\b N+6}\cell{Real}\cell{Output is result R31}\cell\row
\intbl{\b N+7}\cell{Real}\cell{Output is result R32}\cell\row
\intbl{\b N+8}\cell{Real}\cell{Output is result R33}\cell\row\par
#170
\intbl{\b S1}\cell{Matrix A row 1 column 1}\cell\row
\intbl{\b S2}\cell{Matrix A row 1 column 2}\cell\row
\intbl{\b S3}\cell{Matrix A row 1 column 3}\cell\row
\intbl{\b S4}\cell{Matrix A row 2 column 1}\cell\row
\intbl{\b S5}\cell{Matrix A row 2 column 2}\cell\row
\intbl{\b S6}\cell{Matrix A row 2 column 3}\cell\row
\intbl{\b S7}\cell{Matrix A row 3 column 1}\cell\row
\intbl{\b S8}\cell{Matrix A row 3 column 2}\cell\row
\intbl{\b S9}\cell{Matrix A row 3 column 3}\cell\row
\intbl{\b S10}\cell{Matrix B row 1 column 1}\cell\row
\intbl{\b S11}\cell{Matrix B row 1 column 2}\cell\row
\intbl{\b S12}\cell{Matrix B row 1 column 3}\cell\row
\intbl{\b S13}\cell{Matrix B row 2 column 1}\cell\row
\intbl{\b S14}\cell{Matrix B row 2 column 2}\cell\row
\intbl{\b S15}\cell{Matrix B row 2 column 3}\cell\row
\intbl{\b S16}\cell{Matrix B row 3 column 1}\cell\row
\intbl{\b S17}\cell{Matrix B row 3 column 2}\cell\row
\intbl{\b S18}\cell{Matrix B row 3 column 3}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is result R11}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is result R12}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is result R13}\cell\row
\intbl{\b N+3}\cell{Real}\cell{Output is result R21}\cell\row
\intbl{\b N+4}\cell{Real}\cell{Output is result R22}\cell\row
\intbl{\b N+5}\cell{Real}\cell{Output is result R23}\cell\row
\intbl{\b N+6}\cell{Real}\cell{Output is result R31}\cell\row
\intbl{\b N+7}\cell{Real}\cell{Output is result R32}\cell\row
\intbl{\b N+8}\cell{Real}\cell{Output is result R33}\cell\row\par
#171
\intbl{\b S1}\cell{Input}\cell\row
\intbl{\b S2}\cell{Input units (0-radians 1-degrees)}\cell\row
\intbl{\b S3}\cell{Type 0-sine 1-cosine 2-tangent 3-cotangent 4-secant 5-cosecant}\cell\row
\intbl{\b S4}\cell{(K) gain multiplier}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is trig function value times gain}\cell\row\par
#172
\intbl{\b S1}\cell{Exponent X}\cell\row
\intbl{\b S2}\cell{(K) gain multiplier}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is exponential function value times gain}\cell\row\par
#173
\intbl{\b S1}\cell{Y}\cell\row
\intbl{\b S2}\cell{X}\cell\row
\intbl{\b S3}\cell{(K) gain multiplier}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is power function value (<S1>^<S2>) times gain}\cell\row\par
#174
\intbl{\b S1}\cell{Input}\cell\row
\intbl{\b S2}\cell{Base (0=e 1-10=base 1-10)}\cell\row
\intbl{\b S3}\cell{(K) gain multiplier}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is logarithm function value times gain}\cell\row\par
#175
\intbl{\b S1}\cell{Request to send exception report to RS-232-C port (0=no, 1=yes)}\cell\row
\intbl{\b S2}\cell{Easy step status flag}\cell\row
\intbl{\b S3}\cell{Easy step configuration number of steps}\cell\row
\intbl{\b S4}\cell{Easy step configuration number of inputs}\cell\row
\intbl{\b S5}\cell{Easy step configuration number of outputs}\cell\row
\intbl{\b S6}\cell{Spare 1}\cell\row
\intbl{\b S7}\cell{Spare 2}\cell\row
\intbl{\b S8}\cell{Spare 3}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 0}\cell{Bit}\cell{Output is constant value 0}\cell\row
\intbl{\b 1}\cell{Bit}\cell{Output is constant value 1}\cell\row
\intbl{\b 2}\cell{Bit}\cell{Output is constant value 0 or 0.000}\cell\row
\intbl{\b 3}\cell{Real}\cell{Output is constant value -100.0}\cell\row
\intbl{\b 4}\cell{Real}\cell{Output is constant value -1.0}\cell\row
\intbl{\b 5}\cell{Real}\cell{Output is constant value 0.0}\cell\row
\intbl{\b 6}\cell{Real}\cell{Output is constant value 1.0}\cell\row
\intbl{\b 7}\cell{Real}\cell{Output is constant value 100.0}\cell\row
\intbl{\b 8}\cell{Real}\cell{Output is constant value -9.2 E18}\cell\row
\intbl{\b 9}\cell{Real}\cell{Output is constant value 9.2 E18}\cell\row
\intbl{\b 10}\cell{Bit}\cell{Startup in progress: 0 - no, 1 - yes}\cell\row
\intbl{\b 11}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 12}\cell{Real}\cell{Output is system free time in percent}\cell\row
\intbl{\b 13}\cell{Real}\cell{Output is revision level}\cell\row
\intbl{\b 14}\cell{Real}\cell{Reserved}\cell\row\par
#176
\intbl{\b S1}\cell{Input S1 alarm signal}\cell\row
\intbl{\b S2}\cell{Input S2 alarm signal}\cell\row
\intbl{\b S3}\cell{Input S3 alarm signal}\cell\row
\intbl{\b S4}\cell{Input S4 alarm signal}\cell\row
\intbl{\b S5}\cell{Input S5 alarm signal}\cell\row
\intbl{\b S6}\cell{Input S6 alarm signal}\cell\row
\intbl{\b S7}\cell{Input S7 alarm signal}\cell\row
\intbl{\b S8}\cell{Input S8 alarm signal}\cell\row
\intbl{\b S9}\cell{Input S9 alarm signal}\cell\row
\intbl{\b S10}\cell{Input S10 alarm signal}\cell\row
\intbl{\b S11}\cell{Input S11 alarm signal}\cell\row
\intbl{\b S12}\cell{Input S12 alarm signal}\cell\row
\intbl{\b S13}\cell{Input S13 alarm signal}\cell\row
\intbl{\b S14}\cell{Input S14 alarm signal}\cell\row
\intbl{\b S15}\cell{Input S15 alarm signal}\cell\row
\intbl{\b S16}\cell{Input S16 alarm signal}\cell\row
\intbl{\b S17}\cell{Output S1 device driver block control output status}\cell\row
\intbl{\b S18}\cell{Output S2 device driver block control output status}\cell\row
\intbl{\b S19}\cell{Output S3 device driver block control output status}\cell\row
\intbl{\b S20}\cell{Output S4 device driver block control output status}\cell\row
\intbl{\b S21}\cell{Output S5 device driver block control output status}\cell\row
\intbl{\b S22}\cell{Output S6 device driver block control output status}\cell\row
\intbl{\b S23}\cell{Output S7 device driver block control output status}\cell\row
\intbl{\b S24}\cell{Output S8 device driver block control output status}\cell\row
\intbl{\b S25}\cell{Output S9 device driver block control output status}\cell\row
\intbl{\b S26}\cell{Output S10 device driver block control output status}\cell\row
\intbl{\b S27}\cell{Output S11 device driver block control output status}\cell\row
\intbl{\b S28}\cell{Output S12 device driver block control output status}\cell\row
\intbl{\b S29}\cell{Step jump number}\cell\row
\intbl{\b S30}\cell{Station address}\cell\row
\intbl{\b S31}\cell{Hold/resume}\cell\row
\intbl{\b S32}\cell{I/O utilization}\cell\row
\intbl{\b S33}\cell{Manual override lockout}\cell\row
\intbl{\b S34}\cell{Default mode of outputs}\cell\row
\intbl{\b S35}\cell{Last step number}\cell\row
\intbl{\b S36}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output commands hold or initialize}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is initial step number}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Output indicates alarm acknowledge key depressed}\cell\row\par
#177
\intbl{\b S1}\cell{Engineering units high display reference}\cell\row
\intbl{\b S2}\cell{Engineering units center display reference}\cell\row
\intbl{\b S3}\cell{Engineering units low display reference}\cell\row
\intbl{\b S4}\cell{Engineering units high limit}\cell\row
\intbl{\b S5}\cell{Engineering units low limit}\cell\row
\intbl{\b S6}\cell{Engineering units ID}\cell\row
\intbl{\b S7}\cell{Spare real input}\cell\row
\intbl{\b S8}\cell{Quality state override}\cell\row
\intbl{\b S9}\cell{Input select input}\cell\row
\intbl{\b S10}\cell{Real value input}\cell\row
\intbl{\b S11}\cell{Input shaping algorithm}\cell\row
\intbl{\b S12}\cell{Calculated value input}\cell\row
\intbl{\b S13}\cell{Engineering units user inserted value}\cell\row
\intbl{\b S14}\cell{Permit input select}\cell\row
\intbl{\b S15}\cell{Request to send exception report}\cell\row
\intbl{\b S16}\cell{Alarm suppression enable}\cell\row
\intbl{\b S17}\cell{High 1 alarm}\cell\row
\intbl{\b S18}\cell{Low 1 alarm}\cell\row
\intbl{\b S19}\cell{Deviation alarm}\cell\row
\intbl{\b S20}\cell{Alarm control}\cell\row
\intbl{\b S21}\cell{High alarm deadband}\cell\row
\intbl{\b S22}\cell{High 3 alarm difference}\cell\row
\intbl{\b S23}\cell{High 2 alarm difference}\cell\row
\intbl{\b S24}\cell{High 1 alarm value}\cell\row
\intbl{\b S25}\cell{Low 1 alarm value}\cell\row
\intbl{\b S26}\cell{Low 2 alarm difference}\cell\row
\intbl{\b S27}\cell{Low 3 alarm difference}\cell\row
\intbl{\b S28}\cell{Low alarm deadband (percent)}\cell\row
\intbl{\b S29}\cell{Deviation alarm limit}\cell\row
\intbl{\b S30}\cell{Significant change in engineering units}\cell\row
\intbl{\b S31}\cell{Period for time-based alarms}\cell\row
\intbl{\b S32}\cell{Engineering units high rate of change}\cell\row
\intbl{\b S33}\cell{Engineering units low rate of change}\cell\row
\intbl{\b S34}\cell{Time sequence alarm count limit}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is current value with quality and status}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is current extended status}\cell\row\par
#178
\intbl{\b S1}\cell{Source module address}\cell\row
\intbl{\b S2}\cell{Source block number}\cell\row
\intbl{\b S3}\cell{Source PCU address}\cell\row
\intbl{\b S4}\cell{Source ring number}\cell\row
\intbl{\b S5}\cell{Spare integer specification}\cell\row
\intbl{\b S6}\cell{Spare real specification}\cell\row
\intbl{\b S7}\cell{Spare boolean input}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is current value with quality and status}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is next highest alarm limit}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is next lowest alarm limit}\cell\row
\intbl{\b N+3}\cell{Real}\cell{Output is extended status}\cell\row\par
#179
\intbl{\b S1}\cell{Input}\cell\row
\intbl{\b S2}\cell{Input block type}\cell\row
\intbl{\b S3}\cell{Trending mode}\cell\row
\intbl{\b S4}\cell{Buffer size (number of events)}\cell\row
\intbl{\b S5}\cell{Buffer threshold (percent)}\cell\row
\intbl{\b S6}\cell{Input sampling time (seconds)}\cell\row
\intbl{\b S7}\cell{Significant change (percent)}\cell\row
\intbl{\b S8}\cell{Maximum elapsed time in seconds for event recording}\cell\row
\intbl{\b S9}\cell{Statistical time base period}\cell\row
\intbl{\b S10}\cell{Statistical time base units}\cell\row
\intbl{\b S11}\cell{Maximum elapsed time in seconds for exception reporting}\cell\row
\intbl{\b S12}\cell{Good/suspect threshold}\cell\row
\intbl{\b S13}\cell{Summation conversion factor}\cell\row
\intbl{\b S14}\cell{Summation modifier}\cell\row
\intbl{\b S15}\cell{Block address of statistical time base reset signal}\cell\row
\intbl{\b S16}\cell{Spare}\cell\row
\intbl{\b S17}\cell{Spare}\cell\row
\intbl{\b S18}\cell{Spare}\cell\row
\intbl{\b S19}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is constant 0 with time synchronization status}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is number of minutes of historical data saved buffer.}\cell\row\par
#180
\intbl{\b S1}\cell{Expander bus address}\cell\row
\intbl{\b S2}\cell{Input 1}\cell\row
\intbl{\b S3}\cell{Input 2}\cell\row
\intbl{\b S4}\cell{Input 3}\cell\row
\intbl{\b S5}\cell{Input 4}\cell\row
\intbl{\b S6}\cell{Input 5}\cell\row
\intbl{\b S7}\cell{Input 6}\cell\row
\intbl{\b S8}\cell{Analog output 1}\cell\row
\intbl{\b S9}\cell{Analog output 2}\cell\row
\intbl{\b S10}\cell{Digital output 1}\cell\row
\intbl{\b S11}\cell{Digital output 2}\cell\row
\intbl{\b S12}\cell{Pulse input 1}\cell\row
\intbl{\b S13}\cell{Pulse input 2}\cell\row
\intbl{\b S14}\cell{Failure action (0=trip 1=continue)}\cell\row
\intbl{\b S15}\cell{Spare real input}\cell\row
\intbl{\b S16}\cell{Spare real parameter}\cell\row
\intbl{\b S17}\cell{Spare real parameter}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is value of analog input 1}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is value of analog input 2}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is value of analog input 3}\cell\row
\intbl{\b N+3}\cell{Real}\cell{Output is value of analog input 4}\cell\row
\intbl{\b N+4}\cell{Real}\cell{Output is value of analog input 5}\cell\row
\intbl{\b N+5}\cell{Real}\cell{Output is value of analog input 6}\cell\row
\intbl{\b N+6}\cell{Real}\cell{Output is value of analog output 1}\cell\row
\intbl{\b N+7}\cell{Real}\cell{Output is value of analog output 2}\cell\row
\intbl{\b N+8}\cell{Bit}\cell{Output is value of digital input 1}\cell\row
\intbl{\b N+9}\cell{Bit}\cell{Output is value of digital input 2}\cell\row
\intbl{\b N+10}\cell{Real}\cell{Output is value of pulse input 1}\cell\row
\intbl{\b N+11}\cell{Real}\cell{Output is value of pulse input 2}\cell\row
\intbl{\b N+12}\cell{Bit}\cell{Slave status: 0 - good, 1 - bad}\cell\row
\intbl{\b N+13}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b N+14}\cell{Real}\cell{Reserved}\cell\row\par
#181
\intbl{\b S1}\cell{BATCH I/O block}\cell\row
\intbl{\b S2}\cell{Block address manual/auto station loop 1}\cell\row
\intbl{\b S3}\cell{Block address manual/auto station loop 2}\cell\row
\intbl{\b S4}\cell{Output status 1}\cell\row
\intbl{\b S5}\cell{Output status 2}\cell\row
\intbl{\b S6}\cell{Auxiliary input 1}\cell\row
\intbl{\b S7}\cell{Auxiliary input 2}\cell\row
\intbl{\b S8}\cell{External alarm 1}\cell\row
\intbl{\b S9}\cell{External alarm 2}\cell\row
\intbl{\b S10}\cell{ASCII string descriptor}\cell\row
\intbl{\b S11}\cell{Current step number}\cell\row
\intbl{\b S12}\cell{CBC station link address}\cell\row
\intbl{\b S13}\cell{Run/hold signal}\cell\row
\intbl{\b S14}\cell{Manual override lockout}\cell\row
\intbl{\b S15}\cell{Default mode of outputs}\cell\row
\intbl{\b S16}\cell{Emergency stop lockout}\cell\row
\intbl{\b S17}\cell{Display (0-step,1-setpoint)}\cell\row
\intbl{\b S18}\cell{Last step number}\cell\row
\intbl{\b S19}\cell{Spare integer parameter}\cell\row
\intbl{\b S20}\cell{Spare real parameter}\cell\row
\intbl{\b S21}\cell{Spare real parameter}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output commands hold or initialize}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is initial step number}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is recipe number}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Output is value of F1 key}\cell\row
\intbl{\b N+4}\cell{Bit}\cell{Output is value of F2 key}\cell\row
\intbl{\b N+5}\cell{Bit}\cell{Output is value of auxiliary switch 1}\cell\row
\intbl{\b N+6}\cell{Bit}\cell{Output is value of auxiliary switch 2}\cell\row
\intbl{\b N+7}\cell{Bit}\cell{Output is value of auxiliary switch 3}\cell\row
\intbl{\b N+8}\cell{Bit}\cell{Output is value of auxiliary switch 4}\cell\row
\intbl{\b N+9}\cell{Bit}\cell{Output is value of auxiliary switch 5}\cell\row
\intbl{\b N+10}\cell{Bit}\cell{Output is value of auxiliary switch 6}\cell\row
\intbl{\b N+11}\cell{Bit}\cell{Output is value of auxiliary switch 7}\cell\row
\intbl{\b N+12}\cell{Bit}\cell{Output is value of auxiliary switch 8}\cell\row
\intbl{\b N+13}\cell{Bit}\cell{Output indicates alarm ack key depressed}\cell\row
\intbl{\b N+14}\cell{Bit}\cell{Output indicates alarm status}\cell\row
\intbl{\b N+15}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b N+16}\cell{Real}\cell{Reserved}\cell\row\par
#182
\intbl{\b S1}\cell{Input type}\cell\row
\intbl{\b S2}\cell{Engineering units type}\cell\row
\intbl{\b S3}\cell{Reserved (calibration)}\cell\row
\intbl{\b S4}\cell{Engineering units zero of input}\cell\row
\intbl{\b S5}\cell{Engineering units span of input}\cell\row
\intbl{\b S6}\cell{Leadwire resistance}\cell\row
\intbl{\b S7}\cell{Offset correction factor}\cell\row
\intbl{\b S8}\cell{Gain correction factor}\cell\row
\intbl{\b S9}\cell{Polynomial block}\cell\row
\intbl{\b S10}\cell{Cold junction}\cell\row
\intbl{\b S11}\cell{Polynomial calculation option}\cell\row
\intbl{\b S12}\cell{Lag filter time (sec)}\cell\row
\intbl{\b S13}\cell{Spare real parameter}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output value is input in millivolts with quality}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is analog input status}\cell\row\par
#183
\intbl{\b S1}\cell{Block address of RS-232-C output request}\cell\row
\intbl{\b S2}\cell{Easy step plus status}\cell\row
\intbl{\b S3}\cell{Number of steps configured}\cell\row
\intbl{\b S4}\cell{Number of recipes configured}\cell\row
\intbl{\b S5}\cell{Number of digital I/O in the CBC configured with easy step plus}\cell\row
\intbl{\b S6}\cell{Number of digital I/O in the CSC configured with easy step plus}\cell\row
\intbl{\b S7}\cell{Number of analog I/O configured with easy step plus}\cell\row
\intbl{\b S8}\cell{Number of pulse inputs configured with easy step plus}\cell\row
\intbl{\b S9}\cell{Spare real parameter}\cell\row
\intbl{\b S10}\cell{Spare real parameter}\cell\row
\intbl{\b S11}\cell{Module bus address of unit solving the recipe tables for easy step plus}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 0}\cell{Bit}\cell{Output is constant 0}\cell\row
\intbl{\b 1}\cell{Bit}\cell{Output is constant 1}\cell\row
\intbl{\b 2}\cell{Real}\cell{Output is constant 0 or 0.0}\cell\row
\intbl{\b 3}\cell{Real}\cell{Output is constant -100.0}\cell\row
\intbl{\b 4}\cell{Real}\cell{Output is constant -1.0}\cell\row
\intbl{\b 5}\cell{Real}\cell{Output is constant 0.0}\cell\row
\intbl{\b 6}\cell{Real}\cell{Output is constant 1.0}\cell\row
\intbl{\b 7}\cell{Real}\cell{Output is constant 100.0}\cell\row
\intbl{\b 8}\cell{Real}\cell{Output is constant -9.2 E18}\cell\row
\intbl{\b 9}\cell{Real}\cell{Output is constant 9.2 E18}\cell\row
\intbl{\b 10}\cell{Bit}\cell{Startup in progress: 0 - startup complete, 1 - startup in progress}\cell\row
\intbl{\b 11}\cell{Integer}\cell{Reserved}\cell\row
\intbl{\b 12}\cell{Real}\cell{Output is system tree time in percent}\cell\row
\intbl{\b 13}\cell{Real}\cell{Output is revision level}\cell\row
\intbl{\b 14}\cell{Real}\cell{Reserved}\cell\row\par
#184
\intbl{\b S1}\cell{Primary slave address}\cell\row
\intbl{\b S2}\cell{Secondary slave address}\cell\row
\intbl{\b S3}\cell{Analog input subscriber block}\cell\row
\intbl{\b S4}\cell{Digital input subscriber block}\cell\row
\intbl{\b S5}\cell{Analog output subscriber block}\cell\row
\intbl{\b S6}\cell{Digital output subscriber block}\cell\row
\intbl{\b S7}\cell{FIP transmitter definition}\cell\row
\intbl{\b S8}\cell{Bus arbitrator}\cell\row
\intbl{\b S9}\cell{Failure action (0=trip 1=continue)}\cell\row
\intbl{\b S10}\cell{Synchronization ID}\cell\row
\intbl{\b S11}\cell{Promptitude period}\cell\row
\intbl{\b S12}\cell{Window}\cell\row
\intbl{\b S13}\cell{Number of synchronization subsystem}\cell\row
\intbl{\b S14}\cell{Timer control}\cell\row
\intbl{\b S15}\cell{Fieldbus segment number}\cell\row
\intbl{\b S16}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output indicates primary slave status with alarm}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Output indicates secondary slave status with alarm}\cell\row\par
#185
\intbl{\b S1}\cell{Next digital input subscriber block}\cell\row
\intbl{\b S2}\cell{FIP variable identifier}\cell\row
\intbl{\b S3}\cell{Group number}\cell\row
\intbl{\b S4}\cell{Input type}\cell\row
\intbl{\b S5}\cell{Asynchronous (promptitude) refresh period (msec)}\cell\row
\intbl{\b S6}\cell{Synchronous (window) refresh period (msec)}\cell\row
\intbl{\b S7}\cell{Aperiodic variable / periodic variable}\cell\row
\intbl{\b S8}\cell{Refresh: (0=disabled, 1= synchronous, 2=asynchronous, 3=punctual (both))}\cell\row
\intbl{\b S9}\cell{Spare}\cell\row
\intbl{\b S10}\cell{Spare}\cell\row
\intbl{\b S11}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is value of digital input 1 with quality}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Output is value of digital input 2 with quality}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Output is value of digital input 3 with quality}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Output is value of digital input 4 with quality}\cell\row
\intbl{\b N+4}\cell{Bit}\cell{Output is value of digital input 5 with quality}\cell\row
\intbl{\b N+5}\cell{Bit}\cell{Output is value of digital input 6 with quality}\cell\row
\intbl{\b N+6}\cell{Bit}\cell{Output is value of digital input 7 with quality}\cell\row
\intbl{\b N+7}\cell{Bit}\cell{Output is value of digital input 8 with quality}\cell\row\par
#186
\intbl{\b S1}\cell{Next analog input subscriber block}\cell\row
\intbl{\b S2}\cell{FIP variable identifier}\cell\row
\intbl{\b S3}\cell{Group number}\cell\row
\intbl{\b S4}\cell{Input type}\cell\row
\intbl{\b S5}\cell{Asynchronous (promptitude) refresh period (msec)}\cell\row
\intbl{\b S6}\cell{Synchronous (window) refresh period (msec)}\cell\row
\intbl{\b S7}\cell{Aperiodic variable / periodic variable}\cell\row
\intbl{\b S8}\cell{Refresh: (0=disabled, 1= synchronous, 2=asynchronous, 3=punctual (both))}\cell\row
\intbl{\b S9}\cell{Spare}\cell\row
\intbl{\b S10}\cell{Spare}\cell\row
\intbl{\b S11}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is value of analog input 1 with quality}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is value of analog input 2 with quality}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is value of analog input 3 with quality}\cell\row
\intbl{\b N+3}\cell{Real}\cell{Output is value of analog input 4 with quality}\cell\row
\intbl{\b N+4}\cell{Real}\cell{Output is value of analog input 5 with quality}\cell\row
\intbl{\b N+5}\cell{Real}\cell{Output is value of analog input 6 with quality}\cell\row
\intbl{\b N+6}\cell{Real}\cell{Output is value of analog input 7 with quality}\cell\row
\intbl{\b N+7}\cell{Real}\cell{Output is value of analog input 8 with quality}\cell\row\par
#187
\intbl{\b S1}\cell{Next analog output subscriber block}\cell\row
\intbl{\b S2}\cell{FIP variable identifier}\cell\row
\intbl{\b S3}\cell{Group number}\cell\row
\intbl{\b S4}\cell{Output 1}\cell\row
\intbl{\b S5}\cell{Output 2}\cell\row
\intbl{\b S6}\cell{Output 3}\cell\row
\intbl{\b S7}\cell{Output 4}\cell\row
\intbl{\b S8}\cell{Output 5}\cell\row
\intbl{\b S9}\cell{Output 6}\cell\row
\intbl{\b S10}\cell{Output 7}\cell\row
\intbl{\b S11}\cell{Output 8}\cell\row
\intbl{\b S12}\cell{Output type}\cell\row
\intbl{\b S13}\cell{Asynchronous (promptitude) refresh period (msec)}\cell\row
\intbl{\b S14}\cell{Synchronous (window) refresh period (msec)}\cell\row
\intbl{\b S15}\cell{Aperiodic variable / periodic variable}\cell\row
\intbl{\b S16}\cell{Refresh: (0=disabled, 1= synchronous, 2=asynchronous, 3=punctual (both))}\cell\row
\intbl{\b S17}\cell{Spare}\cell\row
\intbl{\b S18}\cell{Spare}\cell\row
\intbl{\b S19}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is quality of output}\cell\row\par
#188
\intbl{\b S1}\cell{Next digital output subscriber block}\cell\row
\intbl{\b S2}\cell{FIP variable identifier}\cell\row
\intbl{\b S3}\cell{Group number}\cell\row
\intbl{\b S4}\cell{Output 1}\cell\row
\intbl{\b S5}\cell{Output 2}\cell\row
\intbl{\b S6}\cell{Output 3}\cell\row
\intbl{\b S7}\cell{Output 4}\cell\row
\intbl{\b S8}\cell{Output 5}\cell\row
\intbl{\b S9}\cell{Output 6}\cell\row
\intbl{\b S10}\cell{Output 7}\cell\row
\intbl{\b S11}\cell{Output 8}\cell\row
\intbl{\b S12}\cell{Output type}\cell\row
\intbl{\b S13}\cell{Asynchronous (promptitude) refresh period (msec)}\cell\row
\intbl{\b S14}\cell{Synchronous (window) refresh period (msec)}\cell\row
\intbl{\b S15}\cell{Aperiodic variable / periodic variable}\cell\row
\intbl{\b S16}\cell{Refresh: (0=disabled, 1= synchronous, 2=asynchronous, 3=punctual (both))}\cell\row
\intbl{\b S17}\cell{Spare}\cell\row
\intbl{\b S18}\cell{Spare}\cell\row
\intbl{\b S19}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is quality of output}\cell\row\par
#189
#190
\intbl{\b S1}\cell{UDF program ID}\cell\row
\intbl{\b S2}\cell{UDF program size (10 byte increments)}\cell\row
\intbl{\b S3}\cell{Tunable real parameter}\cell\row
\intbl{\b S4}\cell{Tunable real parameter}\cell\row
\intbl{\b S5}\cell{Tunable real parameter}\cell\row
\intbl{\b S6}\cell{Tunable real parameter}\cell\row
\intbl{\b S7}\cell{Spare}\cell\row
\intbl{\b S8}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Reserved}\cell\row\par
#191
\intbl{\b S1}\cell{Block address of any input}\cell\row
\intbl{\b S2}\cell{Block address of any input}\cell\row
\intbl{\b S3}\cell{Block address of any input}\cell\row
\intbl{\b S4}\cell{Block address of any input}\cell\row
\intbl{\b S5}\cell{Block address of any input}\cell\row
\intbl{\b S6}\cell{Block address of any input}\cell\row
\intbl{\b S7}\cell{Block address of any input}\cell\row
\intbl{\b S8}\cell{Block address of any input}\cell\row
\intbl{\b S9}\cell{Tunable real parameter}\cell\row
\intbl{\b S10}\cell{Tunable real parameter}\cell\row
\intbl{\b S11}\cell{Tunable real parameter}\cell\row
\intbl{\b S12}\cell{Tunable real parameter}\cell\row
\intbl{\b S13}\cell{Tunable real parameter}\cell\row
\intbl{\b S14}\cell{Tunable real parameter}\cell\row
\intbl{\b S15}\cell{Block address of first auxiliary UDF}\cell\row
\intbl{\b S16}\cell{Size of data (in bytes)}\cell\row
\intbl{\b S17}\cell{UDF declaration}\cell\row
\intbl{\b S18}\cell{Spare}\cell\row
\intbl{\b S19}\cell{Spare}\cell\row
\intbl{\b S20}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is user real output value 1}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is user real output value 2}\cell\row\par
#192
\intbl{\b S1}\cell{Block address of any input}\cell\row
\intbl{\b S2}\cell{Block address of any input}\cell\row
\intbl{\b S3}\cell{Block address of any input}\cell\row
\intbl{\b S4}\cell{Block address of any input}\cell\row
\intbl{\b S5}\cell{Block address of any input}\cell\row
\intbl{\b S6}\cell{Block address of any input}\cell\row
\intbl{\b S7}\cell{Block address of any input}\cell\row
\intbl{\b S8}\cell{Block address of any input}\cell\row
\intbl{\b S9}\cell{Block address of any input}\cell\row
\intbl{\b S10}\cell{Block address of any input}\cell\row
\intbl{\b S11}\cell{Block address of any input}\cell\row
\intbl{\b S12}\cell{Block address of any input}\cell\row
\intbl{\b S13}\cell{Block address of any input}\cell\row
\intbl{\b S14}\cell{Block address of any input}\cell\row
\intbl{\b S15}\cell{Block address of any input}\cell\row
\intbl{\b S16}\cell{Block address of any input}\cell\row
\intbl{\b S17}\cell{Block address of any input}\cell\row
\intbl{\b S18}\cell{Block address of any input}\cell\row
\intbl{\b S19}\cell{Tunable real parameter}\cell\row
\intbl{\b S20}\cell{Tunable real parameter}\cell\row
\intbl{\b S21}\cell{Tunable real parameter}\cell\row
\intbl{\b S22}\cell{Tunable real parameter}\cell\row
\intbl{\b S23}\cell{Block address of first auxiliary UDF}\cell\row
\intbl{\b S24}\cell{Size of data (in bytes)}\cell\row
\intbl{\b S25}\cell{UDF declaration}\cell\row
\intbl{\b S26}\cell{Spare}\cell\row
\intbl{\b S27}\cell{Spare}\cell\row
\intbl{\b S28}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is user digital output value 1}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Output is user digital output value 2}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Output is user digital output value 3}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Output is user digital output value 4}\cell\row
\intbl{\b N+4}\cell{Bit}\cell{Output is user digital output value 5}\cell\row
\intbl{\b N+5}\cell{Bit}\cell{Output is user digital output value 6}\cell\row
\intbl{\b N+6}\cell{Bit}\cell{Output is user digital output value 7}\cell\row
\intbl{\b N+7}\cell{Bit}\cell{Output is user digital output value 8}\cell\row
\intbl{\b N+8}\cell{Real}\cell{Output is user real output value 1}\cell\row
\intbl{\b N+9}\cell{Real}\cell{Output is user real output value 2}\cell\row\par
#193
\intbl{\b S1}\cell{Source module address}\cell\row
\intbl{\b S2}\cell{Source block number}\cell\row
\intbl{\b S3}\cell{Source PCU address}\cell\row
\intbl{\b S4}\cell{Source loop address}\cell\row
\intbl{\b S5}\cell{Maximum data space allocation}\cell\row
\intbl{\b S6}\cell{Engineering units}\cell\row
\intbl{\b S7}\cell{Start control}\cell\row
\intbl{\b S8}\cell{Spare}\cell\row
\intbl{\b S9}\cell{Spare}\cell\row
\intbl{\b S10}\cell{Spare}\cell\row
\intbl{\b S11}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{User}\cell{Output is user defined data with status and quality}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output indicates block status}\cell\row\par
#194
\intbl{\b S1}\cell{Input data}\cell\row
\intbl{\b S2}\cell{Input control}\cell\row
\intbl{\b S3}\cell{Input status}\cell\row
\intbl{\b S4}\cell{Maximum data space allocation}\cell\row
\intbl{\b S5}\cell{Engineering units}\cell\row
\intbl{\b S6}\cell{Start control}\cell\row
\intbl{\b S7}\cell{Re-alarm timeout time (sec)}\cell\row
\intbl{\b S8}\cell{Spare}\cell\row
\intbl{\b S9}\cell{Spare}\cell\row
\intbl{\b S10}\cell{Spare}\cell\row
\intbl{\b S11}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{User }\cell{Output is user defined data with status and quality}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output indicates block status}\cell\row\par
#195
#196
#197
#198
\intbl{\b S1}\cell{Block address of any input}\cell\row
\intbl{\b S2}\cell{Block address of any input}\cell\row
\intbl{\b S3}\cell{Block address of any input}\cell\row
\intbl{\b S4}\cell{Block address of any input}\cell\row
\intbl{\b S5}\cell{Tunable real parameter}\cell\row
\intbl{\b S6}\cell{Tunable real parameter}\cell\row
\intbl{\b S7}\cell{Tunable real parameter}\cell\row
\intbl{\b S8}\cell{Tunable real parameter}\cell\row
\intbl{\b S9}\cell{Block address of next auxiliary UDF}\cell\row
\intbl{\b S10}\cell{Spare}\cell\row
\intbl{\b S11}\cell{Spare}\cell\row
\intbl{\b S12}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is user real value 1}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is user real value 2}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is user real value 3}\cell\row
\intbl{\b N+3}\cell{Real}\cell{Output is user real value 4}\cell\row\par
#199
\intbl{\b S1}\cell{Block address of any input}\cell\row
\intbl{\b S2}\cell{Block address of any input}\cell\row
\intbl{\b S3}\cell{Block address of any input}\cell\row
\intbl{\b S4}\cell{Block address of any input}\cell\row
\intbl{\b S5}\cell{Tunable real parameter}\cell\row
\intbl{\b S6}\cell{Tunable real parameter}\cell\row
\intbl{\b S7}\cell{Tunable real parameter}\cell\row
\intbl{\b S8}\cell{Tunable real parameter}\cell\row
\intbl{\b S9}\cell{Block address of next auxiliary UDF}\cell\row
\intbl{\b S10}\cell{Spare}\cell\row
\intbl{\b S11}\cell{Spare}\cell\row
\intbl{\b S12}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is user digital value 1}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Output is user digital value 2}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Output is user digital value 3}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Output is user digital value 4}\cell\row\par
#200
\intbl{\b S1}\cell{Configuration lock/1=lock 0=unlock}\cell\row
\intbl{\b S2}\cell{Redirection ring number}\cell\row
\intbl{\b S3}\cell{Redirection node number}\cell\row
\intbl{\b S4}\cell{Redirection module number}\cell\row
\intbl{\b S5}\cell{INFI-NET exception report poll rate (msec)}\cell\row
\intbl{\b S6}\cell{Plant Loop exception report poll rate (msec)}\cell\row
\intbl{\b S7}\cell{Cross loop time synchronization}\cell\row
\intbl{\b S8}\cell{Spare}\cell\row
\intbl{\b S9}\cell{Spare}\cell\row
\intbl{\b S10}\cell{Spare}\cell\row
\intbl{\b S11}\cell{Spare}\cell\row
\intbl{\b S12}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 1}\cell{Real}\cell{Output is number of incoming INFI-NET exception reports per second}\cell\row
\intbl{\b 2}\cell{Real}\cell{Output is number of outgoing INFI-NET exception reports per second}\cell\row
\intbl{\b 3}\cell{Real}\cell{Output is number of incoming Plant Loop exception reports per second}\cell\row
\intbl{\b 4}\cell{Real}\cell{Output is number of outgoing Plant Loop exception reports per second}\cell\row
\intbl{\b 5}\cell{Real}\cell{Output is amount of RAM available}\cell\row
\intbl{\b 6}\cell{Real}\cell{Output is amount of NVRAM available}\cell\row
\intbl{\b 7}\cell{Real}\cell{Output is revision level}\cell\row
\intbl{\b 8}\cell{Real}\cell{Output is CPU free time in percent}\cell\row
\intbl{\b 9}\cell{Real}\cell{Output is time and date synchronization state}\cell\row
\intbl{\b 10}\cell{Real}\cell{Output is current hour of day (0 - 23)}\cell\row
\intbl{\b 11}\cell{Real}\cell{Output is current minutes of hour (0 - 59)}\cell\row
\intbl{\b 12}\cell{Real}\cell{Output is current seconds of minute (0 - 59)}\cell\row
\intbl{\b 13}\cell{Real}\cell{Output is current year (0 - 99)}\cell\row
\intbl{\b 14}\cell{Real}\cell{Output is current month (1 - 12)}\cell\row
\intbl{\b 15}\cell{Real}\cell{Output is current day (1 - 31)}\cell\row
\intbl{\b 16}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 17}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 18}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 19}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 20}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 21}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 22}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 23}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 24}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 25}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 26}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 27}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 28}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 29}\cell{Real}\cell{Reserved}\cell\row\par
#201
\intbl{\b S1}\cell{Import data type}\cell\row
\intbl{\b S2}\cell{Source ring}\cell\row
\intbl{\b S3}\cell{Source node}\cell\row
\intbl{\b S4}\cell{Source module}\cell\row
\intbl{\b S5}\cell{Source block}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Integer}\cell{Output is block status}\cell\row\par
#202
\intbl{\b S1}\cell{Port 1 transmission start delay after transmitter turned on (msec)}\cell\row
\intbl{\b S2}\cell{Port 1 transmitter turn off delay after transmission sent (msec)}\cell\row
\intbl{\b S3}\cell{Port 2 transmission start delay after transmitter turned on (msec)}\cell\row
\intbl{\b S4}\cell{Port 2 transmitter turn off delay after transmission sent (msec)}\cell\row
\intbl{\b S5}\cell{Port 1 maximum transmission duration (msec)}\cell\row
\intbl{\b S6}\cell{Port 2 maximum transmission duration (msec)}\cell\row
\intbl{\b S7}\cell{Port 1 communication status watchdog timer (seconds)}\cell\row
\intbl{\b S8}\cell{Port 2 communication status watchdog timer (seconds)}\cell\row
\intbl{\b S9}\cell{Port 1 baud rate}\cell\row
\intbl{\b S10}\cell{Port 2 baud rate}\cell\row
\intbl{\b S11}\cell{Port 1 data characteristics}\cell\row
\intbl{\b S12}\cell{Port 2 data characteristics}\cell\row
\intbl{\b S13}\cell{Port 1 duplex mode}\cell\row
\intbl{\b S14}\cell{Port 2 duplex mode}\cell\row
\intbl{\b S15}\cell{Port 2 mode}\cell\row
\intbl{\b S16}\cell{Failure error rate}\cell\row
\intbl{\b S17}\cell{Action on communication equipment fail}\cell\row
\intbl{\b S18}\cell{Exception reporting rate}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 1}\cell{Bit}\cell{Output is port 1 communication status}\cell\row
\intbl{\b 2}\cell{Bit}\cell{Output is port 2 communication status}\cell\row
\intbl{\b 3}\cell{Integer}\cell{Spare}\cell\row
\intbl{\b 4}\cell{Integer}\cell{Spare}\cell\row
\intbl{\b 5}\cell{Integer}\cell{Spare}\cell\row
\intbl{\b 6}\cell{Integer}\cell{Spare}\cell\row\par
#203
\intbl{\b S1}\cell{Configuration lock}\cell\row
\intbl{\b S2}\cell{Redirection loop address}\cell\row
\intbl{\b S3}\cell{Redirection node}\cell\row
\intbl{\b S4}\cell{Redirection module}\cell\row
\intbl{\b S5}\cell{Exception report poll rate}\cell\row
\intbl{\b S6}\cell{Cross loop time sync}\cell\row
\intbl{\b S7}\cell{Reply delay after transmission on (port 1)}\cell\row
\intbl{\b S8}\cell{Transmission turn-off delay (port 1)}\cell\row
\intbl{\b S9}\cell{Reply delay after transmission on (port 2)}\cell\row
\intbl{\b S10}\cell{Transmission turn-off delay (port 2)}\cell\row
\intbl{\b S11}\cell{Maximum transmit duration (port 1)}\cell\row
\intbl{\b S12}\cell{Maximum transmit duration (port 2)}\cell\row
\intbl{\b S13}\cell{Communication status watchdog timer (port 1)}\cell\row
\intbl{\b S14}\cell{Communication status watchdog timer (port 2)}\cell\row
\intbl{\b S15}\cell{Duplex mode (port 1)}\cell\row
\intbl{\b S16}\cell{Duplex mode (port 2)}\cell\row
\intbl{\b S17}\cell{Usage rules (port 2)}\cell\row
\intbl{\b S18}\cell{Acceptable link error rate}\cell\row
\intbl{\b S19}\cell{Action on communication equipment fail}\cell\row
\intbl{\b S20}\cell{Equipment select output initial state}\cell\row
\intbl{\b S21}\cell{Baud rate (port 1)}\cell\row
\intbl{\b S22}\cell{Baud rate (port 2)}\cell\row
\intbl{\b S23}\cell{Data characteristics (port 1)}\cell\row
\intbl{\b S24}\cell{Data characteristics (port 2)}\cell\row
\intbl{\b S25}\cell{RS232 characteristics}\cell\row
\intbl{\b S26}\cell{Remote loop address}\cell\row
\intbl{\b S27}\cell{Bad quality report delay after link failure}\cell\row
\intbl{\b S28}\cell{Spare}\cell\row
\intbl{\b S29}\cell{Spare}\cell\row
\intbl{\b S30}\cell{Spare}\cell\row
\intbl{\b S31}\cell{Spare}\cell\row
\intbl{\b S32}\cell{Spare}\cell\row
\intbl{\b S33}\cell{Spare}\cell\row
\intbl{\b S34}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 1}\cell{Bit}\cell{Port 1 communication status:\par	0 - good\par	1 with no alarm - error warning\par	1 with alarm - port failed}\cell\row
\intbl{\b 2}\cell{Bit}\cell{Port 2 communication status:\par	0 - good\par	1 with no alarm - error warning\par	1 with alarm - port failed}\cell\row
\intbl{\b 3}\cell{Integer}\cell{Current exception reports transferred per second}\cell\row
\intbl{\b 4}\cell{Integer}\cell{Average exception reports transferred per second}\cell\row
\intbl{\b 5}\cell{Integer}\cell{Maximum exception reports transferred per second}\cell\row
\intbl{\b 6}\cell{Integer}\cell{Current loop exception reports received per second}\cell\row
\intbl{\b 7}\cell{Integer}\cell{Current loop exception reports transmitted per second}\cell\row
\intbl{\b 8}\cell{Integer}\cell{Current link exception reports received per second}\cell\row
\intbl{\b 9}\cell{Integer}\cell{Current link exception reports transmitted pers second}\cell\row
\intbl{\b 10}\cell{Integer}\cell{Available bytes of RAM}\cell\row
\intbl{\b 11}\cell{Integer}\cell{Available bytes of NVRAM}\cell\row
\intbl{\b 12}\cell{Integer}\cell{INIPT02 revision level}\cell\row
\intbl{\b 13}\cell{Integer}\cell{Available percentage of CPU time}\cell\row
\intbl{\b 14}\cell{Integer}\cell{Time and date synchronization state}\cell\row
\intbl{\b 15}\cell{Integer}\cell{Time of day (hours)}\cell\row
\intbl{\b 16}\cell{Integer}\cell{Time of day (minutes)}\cell\row
\intbl{\b 17}\cell{Integer}\cell{Time of day (seconds)}\cell\row
\intbl{\b 18}\cell{Integer}\cell{Calendar (year)}\cell\row
\intbl{\b 19}\cell{Integer}\cell{Calendar (month)}\cell\row
\intbl{\b 20}\cell{Integer}\cell{Calendar (day)}\cell\row
\intbl{\b 21}\cell{Integer}\cell{Port 1 communications error rate in units of 0.1%}\cell\row
\intbl{\b 22}\cell{Integer}\cell{Port 2 communications error rate in units of 0.1%}\cell\row
\intbl{\b 23}\cell{Bit}\cell{Link communication status:\par	0 - good\par	1 with no alarm - error warning\par	1 with alarm - link failed}\cell\row
\intbl{\b 24-29}\cell{Integer}\cell{Unused}\cell\row\par
#204
#205
#206
#207
#208
#209
#210
\intbl{\b S1}\cell{Expander bus slave address 1}\cell\row
\intbl{\b S2}\cell{Expander bus slave address 2}\cell\row
\intbl{\b S3}\cell{Sequence buffer size}\cell\row
\intbl{\b S4}\cell{Event buffer size}\cell\row
\intbl{\b S5}\cell{Age of event data in seconds}\cell\row
\intbl{\b S6}\cell{Input qualifier 1}\cell\row
\intbl{\b S7}\cell{Input qualifier 2}\cell\row
\intbl{\b S8}\cell{Input qualifier 3}\cell\row
\intbl{\b S9}\cell{Input qualifier 4}\cell\row
\intbl{\b S10}\cell{Input qualifier 5}\cell\row
\intbl{\b S11}\cell{Input qualifier 6}\cell\row
\intbl{\b S12}\cell{Input qualifier 7}\cell\row
\intbl{\b S13}\cell{Input qualifier 8}\cell\row
\intbl{\b S14}\cell{Input qualifier 9}\cell\row
\intbl{\b S15}\cell{Input qualifier 10}\cell\row
\intbl{\b S16}\cell{Input qualifier 11}\cell\row
\intbl{\b S17}\cell{Input qualifier 12}\cell\row
\intbl{\b S18}\cell{Input qualifier 13}\cell\row
\intbl{\b S19}\cell{Input qualifier 14}\cell\row
\intbl{\b S20}\cell{Input qualifier 15}\cell\row
\intbl{\b S21}\cell{Input qualifier 16}\cell\row
\intbl{\b S22}\cell{Input qualifier 17}\cell\row
\intbl{\b S23}\cell{Input qualifier 18}\cell\row
\intbl{\b S24}\cell{Input qualifier 19}\cell\row
\intbl{\b S25}\cell{Input qualifier 20}\cell\row
\intbl{\b S26}\cell{Input qualifier 21}\cell\row
\intbl{\b S27}\cell{Input qualifier 22}\cell\row
\intbl{\b S28}\cell{Input qualifier 23}\cell\row
\intbl{\b S29}\cell{Input qualifier 24}\cell\row
\intbl{\b S30}\cell{Input qualifier 25}\cell\row
\intbl{\b S31}\cell{Input qualifier 26}\cell\row
\intbl{\b S32}\cell{Input qualifier 27}\cell\row
\intbl{\b S33}\cell{Input qualifier 28}\cell\row
\intbl{\b S34}\cell{Input qualifier 29}\cell\row
\intbl{\b S35}\cell{Input qualifier 30}\cell\row
\intbl{\b S36}\cell{Input qualifier 31}\cell\row
\intbl{\b S37}\cell{Input qualifier 32}\cell\row
\intbl{\b S38}\cell{Debounce time}\cell\row
\intbl{\b S39}\cell{Snapshot request}\cell\row
\intbl{\b S40}\cell{Summary request}\cell\row
\intbl{\b S41}\cell{Spare boolean input}\cell\row
\intbl{\b S42}\cell{Spare real parameter}\cell\row
\intbl{\b S43}\cell{Spare integer parameter}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output indicates events logged: 0 - no, 1 - yes}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Output is value of input 1 with quality}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Output is value of input 2 with quality}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Output is value of input 3 with quality}\cell\row
\intbl{\b N+4}\cell{Bit}\cell{Output is value of input 4 with quality}\cell\row
\intbl{\b N+5}\cell{Bit}\cell{Output is value of input 5 with quality}\cell\row
\intbl{\b N+6}\cell{Bit}\cell{Output is value of input 6 with quality}\cell\row
\intbl{\b N+7}\cell{Bit}\cell{Output is value of input 7 with quality}\cell\row
\intbl{\b N+8}\cell{Bit}\cell{Output is value of input 8 with quality}\cell\row
\intbl{\b N+9}\cell{Bit}\cell{Output is value of input 9 with quality}\cell\row
\intbl{\b N+10}\cell{Bit}\cell{Output is value of input 10 with quality}\cell\row
\intbl{\b N+11}\cell{Bit}\cell{Output is value of input 11 with quality}\cell\row
\intbl{\b N+12}\cell{Bit}\cell{Output is value of input 12 with quality}\cell\row
\intbl{\b N+13}\cell{Bit}\cell{Output is value of input 13 with quality}\cell\row
\intbl{\b N+14}\cell{Bit}\cell{Output is value of input 14 with quality}\cell\row
\intbl{\b N+15}\cell{Bit}\cell{Output is value of input 15 with quality}\cell\row
\intbl{\b N+16}\cell{Bit}\cell{Output is value of input 16 with quality}\cell\row
\intbl{\b N+17}\cell{Bit}\cell{Output is value of input 17 with quality}\cell\row
\intbl{\b N+18}\cell{Bit}\cell{Output is value of input 18 with quality}\cell\row
\intbl{\b N+19}\cell{Bit}\cell{Output is value of input 19 with quality}\cell\row
\intbl{\b N+20}\cell{Bit}\cell{Output is value of input 20 with quality}\cell\row
\intbl{\b N+21}\cell{Bit}\cell{Output is value of input 21 with quality}\cell\row
\intbl{\b N+22}\cell{Bit}\cell{Output is value of input 22 with quality}\cell\row
\intbl{\b N+23}\cell{Bit}\cell{Output is value of input 23 with quality}\cell\row
\intbl{\b N+24}\cell{Bit}\cell{Output is value of input 24 with quality}\cell\row
\intbl{\b N+25}\cell{Bit}\cell{Output is value of input 25 with quality}\cell\row
\intbl{\b N+26}\cell{Bit}\cell{Output is value of input 26 with quality}\cell\row
\intbl{\b N+27}\cell{Bit}\cell{Output is value of input 27 with quality}\cell\row
\intbl{\b N+28}\cell{Bit}\cell{Output is value of input 28 with quality}\cell\row
\intbl{\b N+29}\cell{Bit}\cell{Output is value of input 29 with quality}\cell\row
\intbl{\b N+30}\cell{Bit}\cell{Output is value of input 30 with quality}\cell\row
\intbl{\b N+31}\cell{Bit}\cell{Output is value of input 31 with quality}\cell\row
\intbl{\b N+32}\cell{Bit}\cell{Output is value of input 32 with quality}\cell\row
\intbl{\b N+33}\cell{Bit}\cell{Slave 1 status: 0 - good, 1 - bad}\cell\row
\intbl{\b N+34}\cell{Bit}\cell{Slave 2 status: 0 - good, 1 - bad}\cell\row
\intbl{\b N+35}\cell{Real}\cell{Sequence of events status: 0.0 - no error, 1.0 - sequence buffer overflow, 2.0 - time synchronization processed}\cell\row\par
#211
\intbl{\b S1}\cell{Input select}\cell\row
\intbl{\b S2}\cell{Permit input select}\cell\row
\intbl{\b S3}\cell{Primary input}\cell\row
\intbl{\b S4}\cell{Alternate input}\cell\row
\intbl{\b S5}\cell{User inserted value}\cell\row
\intbl{\b S6}\cell{Input conditioning mode control}\cell\row
\intbl{\b S7}\cell{Input conditioning time reference (sec)}\cell\row
\intbl{\b S8}\cell{Input conditioning digital filter count reference}\cell\row
\intbl{\b S9}\cell{Alarm mode control}\cell\row
\intbl{\b S10}\cell{Alarm time reference (sec)}\cell\row
\intbl{\b S11}\cell{Alarm digital filter transition count reference}\cell\row
\intbl{\b S12}\cell{Re-alarm/de-alarm time period reference (sec)}\cell\row
\intbl{\b S13}\cell{Alarm suppress enable}\cell\row
\intbl{\b S14}\cell{Quality override input}\cell\row
\intbl{\b S15}\cell{Alarm state latch enable}\cell\row
\intbl{\b S16}\cell{Exception report request}\cell\row
\intbl{\b S17}\cell{User type code}\cell\row
\intbl{\b S18}\cell{Spare}\cell\row
\intbl{\b S19}\cell{Spare input}\cell\row
\intbl{\b S20}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is logic state}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output indicates extended status}\cell\row\par
#212
\intbl{\b S1}\cell{Source module address}\cell\row
\intbl{\b S2}\cell{Source block number}\cell\row
\intbl{\b S3}\cell{Source PCU address}\cell\row
\intbl{\b S4}\cell{Source ring number}\cell\row
\intbl{\b S5}\cell{Spare integer input specification}\cell\row
\intbl{\b S6}\cell{Spare real input specification}\cell\row
\intbl{\b S7}\cell{Spare boolean input}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output is logic level}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output indicates extended status}\cell\row\par
#213
#214
#215
\intbl{\b S1}\cell{Slave address}\cell\row
\intbl{\b S2}\cell{First enhanced analog input definition (FC216)}\cell\row
\intbl{\b S3}\cell{Cold junction reference input (dec C)}\cell\row
\intbl{\b S4}\cell{Failure action 0=trip MFP 1=continue}\cell\row
\intbl{\b S5}\cell{Normal mode rejection type 0=60 hz 1=50 hz}\cell\row
\intbl{\b S6}\cell{Termination device cable length (feet)}\cell\row
\intbl{\b S7}\cell{Spare}\cell\row
\intbl{\b S8}\cell{Spare}\cell\row
\intbl{\b S9}\cell{Spare}\cell\row
\intbl{\b S10}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is cold junction reference temperature}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Slave status: 0 - good, 1 - bad}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is scan cycle time}\cell\row\par
#216
\intbl{\b S1}\cell{Slave address}\cell\row
\intbl{\b S2}\cell{Next enhanced analog input definition}\cell\row
\intbl{\b S3}\cell{Slave input channel number}\cell\row
\intbl{\b S4}\cell{Input signal type}\cell\row
\intbl{\b S5}\cell{Engineering units conversion type 0=deg C 1=deg F}\cell\row
\intbl{\b S6}\cell{Engineering units zero of input}\cell\row
\intbl{\b S7}\cell{Engineering units span of input}\cell\row
\intbl{\b S8}\cell{Input signal range low limit}\cell\row
\intbl{\b S9}\cell{Input signal range high limit}\cell\row
\intbl{\b S10}\cell{Leadwire resistance (ohms)}\cell\row
\intbl{\b S11}\cell{A/D conversion resolution (number of bits)}\cell\row
\intbl{\b S12}\cell{Spare}\cell\row
\intbl{\b S13}\cell{Spare}\cell\row
\intbl{\b S14}\cell{Spare}\cell\row
\intbl{\b S15}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is input value with quality}\cell\row\par
#217
\intbl{\b S1}\cell{Calibration operation code}\cell\row
\intbl{\b S2}\cell{Block address of FC 215 used to configure slave}\cell\row
\intbl{\b S3}\cell{Slave channel number}\cell\row
\intbl{\b S4}\cell{Calibration type}\cell\row
\intbl{\b S5}\cell{Calibration parameter 1}\cell\row
\intbl{\b S6}\cell{Calibration parameter 2}\cell\row
\intbl{\b S7}\cell{Spare}\cell\row
\intbl{\b S8}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is uncorrected value of input}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output indicates channel calibration status}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is gain adjustment}\cell\row
\intbl{\b N+3}\cell{Real}\cell{Output is offset adjustment}\cell\row
\intbl{\b N+4}\cell{Real}\cell{Output indicates calibration command status}\cell\row\par
#218
\intbl{\b S1}\cell{Lead PHASEX block}\cell\row
\intbl{\b S2}\cell{Spare input}\cell\row
\intbl{\b S3}\cell{Spare input}\cell\row
\intbl{\b S4}\cell{Spare input}\cell\row
\intbl{\b S5}\cell{Block address of abort phase trigger}\cell\row
\intbl{\b S6}\cell{Spare parameter}\cell\row
\intbl{\b S7}\cell{Spare parameter}\cell\row
\intbl{\b S8}\cell{Spare parameter}\cell\row
\intbl{\b S9}\cell{Batch program ID number}\cell\row
\intbl{\b S10}\cell{Debug operation}\cell\row
\intbl{\b S11}\cell{RAM allocation for program object file (1K byte increments)}\cell\row
\intbl{\b S12}\cell{RAM allocation for phase data(1 byte increments)}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Current state (enumberated value)}\cell\row
\intbl{\b N+1}\cell{E90 string}\cell{Current phase ID}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Fault code}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Abort}\cell\row
\intbl{\b N+4}\cell{Bit}\cell{Acquired status}\cell\row
\intbl{\b N+5}\cell{Real}\cell{Spare}\cell\row
\intbl{\b N+6}\cell{Real}\cell{Spare}\cell\row
\intbl{\b N+7}\cell{Bit}\cell{Spare}\cell\row\par
#219
\intbl{\b S1}\cell{Batch sequence block}\cell\row
\intbl{\b S2}\cell{Control mode select}\cell\row
\intbl{\b S3}\cell{Reserve allow input}\cell\row
\intbl{\b S4}\cell{Ownership allow input}\cell\row
\intbl{\b S5}\cell{Spare real input}\cell\row
\intbl{\b S6}\cell{Spare real input}\cell\row
\intbl{\b S7}\cell{Spare real input}\cell\row
\intbl{\b S8}\cell{Spare boolean input}\cell\row
\intbl{\b S9}\cell{Spare boolean input}\cell\row
\intbl{\b S10}\cell{Spare boolean input}\cell\row
\intbl{\b S11}\cell{Status update minimum time (seconds)}\cell\row
\intbl{\b S12}\cell{Status update maximum time (seconds)}\cell\row
\intbl{\b S13}\cell{Maximum number of program connections}\cell\row
\intbl{\b S14}\cell{Spare}\cell\row
\intbl{\b S15}\cell{Spare}\cell\row
\intbl{\b S16}\cell{Spare}\cell\row
\intbl{\b S17}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output is campaign number}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Output is batch number}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Output is lot number}\cell\row
\intbl{\b N+3}\cell{Real}\cell{Output indicates reservation status}\cell\row
\intbl{\b N+4}\cell{Real}\cell{Output indicates ownership status}\cell\row
\intbl{\b N+5}\cell{Real}\cell{Spare}\cell\row
\intbl{\b N+6}\cell{Real}\cell{Spare}\cell\row
\intbl{\b N+7}\cell{Real}\cell{Spare}\cell\row
\intbl{\b N+8}\cell{Real}\cell{Spare}\cell\row
\intbl{\b N+9}\cell{Bit}\cell{Spare}\cell\row\par
#220
\intbl{\b S1}\cell{Historian #1 expected (0=no, 1=yes)}\cell\row
\intbl{\b S2}\cell{Historian #2 expected (0=no, 1=yes)}\cell\row
\intbl{\b S3}\cell{Historian #3 expected (0=no, 1=yes)}\cell\row
\intbl{\b S4}\cell{Historian #4 expected (0=no, 1=yes)}\cell\row
\intbl{\b S5}\cell{Historian #5 expected (0=no, 1=yes)}\cell\row
\intbl{\b S6}\cell{Historian #6 expected (0=no, 1=yes)}\cell\row
\intbl{\b S7}\cell{Historian #7 expected (0=no, 1=yes)}\cell\row
\intbl{\b S8}\cell{Historian #8 expected (0=no, 1=yes)}\cell\row
\intbl{\b S9}\cell{Error action}\cell\row
\intbl{\b S10}\cell{Timeout time (sec)}\cell\row
\intbl{\b S11}\cell{Buffer size (bytes)}\cell\row
\intbl{\b S12}\cell{Block address of BSEQ block}\cell\row
\intbl{\b S13}\cell{Campaign number input}\cell\row
\intbl{\b S14}\cell{Batch number input}\cell\row
\intbl{\b S15}\cell{Lot number input}\cell\row
\intbl{\b S16}\cell{Check ID input}\cell\row
\intbl{\b S17}\cell{Spare input}\cell\row
\intbl{\b S18}\cell{Spare input}\cell\row
\intbl{\b S19}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Summary status: 0 - not all bad, 1 - all bad}\cell\row
\intbl{\b N+1}\cell{Real}\cell{Historian 1 status: -1 - not expected, 0 - good, 1 - bad}\cell\row
\intbl{\b N+2}\cell{Real}\cell{Historian 2 status: -1 - not expected, 0 - good, 1 - bad}\cell\row
\intbl{\b N+3}\cell{Real}\cell{Historian 3 status: -1 - not expected, 0 - good, 1 - bad}\cell\row
\intbl{\b N+4}\cell{Real}\cell{Historian 4 status: -1 - not expected, 0 - good, 1 - bad}\cell\row
\intbl{\b N+5}\cell{Real}\cell{Historian 5 status: -1 - not expected, 0 - good, 1 - bad}\cell\row
\intbl{\b N+6}\cell{Real}\cell{Historian 6 status: -1 - not expected, 0 - good, 1 - bad}\cell\row
\intbl{\b N+7}\cell{Real}\cell{Historian 7 status: -1 - not expected, 0 - good, 1 - bad}\cell\row
\intbl{\b N+8}\cell{Real}\cell{Historian 8 status: -1 - not expected, 0 - good, 1 - bad}\cell\row
\intbl{\b N+9}\cell{Real}\cell{Output is campaign number}\cell\row
\intbl{\b N+10}\cell{Real}\cell{Output is batch number}\cell\row
\intbl{\b N+11}\cell{Real}\cell{Output is lot number}\cell\row
\intbl{\b N+12}\cell{Real}\cell{Output is event number}\cell\row
\intbl{\b N+13}\cell{Real}\cell{Spare}\cell\row\par
#221
\intbl{\b S1}\cell{32-character device label}\cell\row
\intbl{\b S2}\cell{Block Address of channel 1}\cell\row
\intbl{\b S3}\cell{Block Address of channel 2}\cell\row
\intbl{\b S4}\cell{Block Address of channel 3}\cell\row
\intbl{\b S5}\cell{Block Address of channel 4}\cell\row
\intbl{\b S6}\cell{Block Address of channel 5}\cell\row
\intbl{\b S7}\cell{Block Address of channel 6}\cell\row
\intbl{\b S8}\cell{Block Address of channel 7}\cell\row
\intbl{\b S9}\cell{Block Address of channel 8}\cell\row
\intbl{\b S10}\cell{Block Address of channel 9}\cell\row
\intbl{\b S11}\cell{Block Address of channel 10}\cell\row
\intbl{\b S12}\cell{Block Address of channel 11}\cell\row
\intbl{\b S13}\cell{Block Address of channel 12}\cell\row
\intbl{\b S14}\cell{Block Address of channel 13}\cell\row
\intbl{\b S15}\cell{Block Address of channel 14}\cell\row
\intbl{\b S16}\cell{Block Address of channel 15}\cell\row
\intbl{\b S17}\cell{Block Address of channel 16}\cell\row
\intbl{\b S18}\cell{Block Address of channel 17}\cell\row
\intbl{\b S19}\cell{Block Address of channel 18}\cell\row
\intbl{\b S20}\cell{Block Address of channel 19}\cell\row
\intbl{\b S21}\cell{Block Address of channel 20}\cell\row
\intbl{\b S22}\cell{Block Address of channel 21}\cell\row
\intbl{\b S23}\cell{Block Address of channel 22}\cell\row
\intbl{\b S24}\cell{Block Address of channel 23}\cell\row
\intbl{\b S25}\cell{Block Address of channel 24}\cell\row
\intbl{\b S26}\cell{Block Address of override/status error inhibit/simulation permit}\cell\row
\intbl{\b S27}\cell{Device status error inhibit}\cell\row
\intbl{\b S28}\cell{Redundant I/O module expected}\cell\row
\intbl{\b S29}\cell{Block address of cold junction reference}\cell\row
\intbl{\b S30}\cell{32-character user scratch area}\cell\row
\intbl{\b S31}\cell{Reserved for future use}\cell\row
\intbl{\b S32}\cell{Reserved for future use}\cell\row
\intbl{\b S33}\cell{Block address of next HSOE device definition}\cell\row
\intbl{\b S34}\cell{Spare}\cell\row
\intbl{\b S35}\cell{Spare}\cell\row
\intbl{\b S36}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Primary I/O block status with quality}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Backup I/O block status with quality}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Channel in override/simulation with quality}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Spare output with quality}\cell\row
\intbl{\b N+4}\cell{Real}\cell{Reserved output with quality}\cell\row\par
#222
\intbl{\b S1}\cell{32-character channel label}\cell\row
\intbl{\b S2}\cell{Input type}\cell\row
\intbl{\b S3}\cell{Engineering units low value}\cell\row
\intbl{\b S4}\cell{Engineering units high value}\cell\row
\intbl{\b S5}\cell{Engineering units identifier}\cell\row
\intbl{\b S6}\cell{Engineering units high alarm}\cell\row
\intbl{\b S7}\cell{Engineering units low alarm}\cell\row
\intbl{\b S8}\cell{Engineering units significant change}\cell\row
\intbl{\b S9}\cell{Block address of input shaping algorithm}\cell\row
\intbl{\b S10}\cell{Engineering unit conversion/shaping algorithm precedence}\cell\row
\intbl{\b S11}\cell{Lead wire resistance}\cell\row
\intbl{\b S12}\cell{A/D conversion average}\cell\row
\intbl{\b S13}\cell{Custom range low limit (in volts)}\cell\row
\intbl{\b S14}\cell{Custom range high limit (in volts)}\cell\row
\intbl{\b S15}\cell{Normal input/undefined}\cell\row
\intbl{\b S16}\cell{Override value}\cell\row
\intbl{\b S17}\cell{Override enable}\cell\row
\intbl{\b S18}\cell{Block address of simulation value}\cell\row
\intbl{\b S19}\cell{Simulation enable}\cell\row
\intbl{\b S20}\cell{Status error inhibit}\cell\row
\intbl{\b S21}\cell{Redundant input deviation limit}\cell\row
\intbl{\b S22}\cell{Length of termination unit cable}\cell\row
\intbl{\b S23}\cell{32-character user scratch area}\cell\row
\intbl{\b S24}\cell{Reserved for future use}\cell\row
\intbl{\b S25}\cell{Spare}\cell\row
\intbl{\b S26}\cell{Spare}\cell\row
\intbl{\b S27}\cell{Spare}\cell\row
\intbl{\b S28}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Analog input value (in specified Eus) with quality}\cell\row\par
#223
\intbl{\b S1}\cell{32-character channel label}\cell\row
\intbl{\b S2}\cell{Block address of value to output}\cell\row
\intbl{\b S3}\cell{Engineering units low value}\cell\row
\intbl{\b S4}\cell{Engineering units high value}\cell\row
\intbl{\b S5}\cell{Engineering units identifier}\cell\row
\intbl{\b S6}\cell{Default state on stall}\cell\row
\intbl{\b S7}\cell{Engineering units high alarm}\cell\row
\intbl{\b S8}\cell{Engineering units low alarm}\cell\row
\intbl{\b S9}\cell{Engineering units significant change}\cell\row
\intbl{\b S10}\cell{A/D conversion accuracy}\cell\row
\intbl{\b S11}\cell{Normal input/undefined}\cell\row
\intbl{\b S12}\cell{Override value}\cell\row
\intbl{\b S13}\cell{Override enable}\cell\row
\intbl{\b S14}\cell{Block address of simulation value}\cell\row
\intbl{\b S15}\cell{Simulation enable}\cell\row
\intbl{\b S16}\cell{Status error inhibit}\cell\row
\intbl{\b S17}\cell{Output deviation limit}\cell\row
\intbl{\b S18}\cell{32-character user scratch area}\cell\row
\intbl{\b S19}\cell{Reserved for future use}\cell\row
\intbl{\b S20}\cell{Spare}\cell\row
\intbl{\b S21}\cell{Spare}\cell\row
\intbl{\b S22}\cell{Spare}\cell\row
\intbl{\b S23}\cell{Spare}\cell\row
\intbl{\b S24}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output value with quality}\cell\row\par
#224
\intbl{\b S1}\cell{32-character channel label}\cell\row
\intbl{\b S2}\cell{Alarm state}\cell\row
\intbl{\b S3}\cell{Debounce period}\cell\row
\intbl{\b S4}\cell{Normal input/undefined}\cell\row
\intbl{\b S5}\cell{Override value}\cell\row
\intbl{\b S6}\cell{Override enable}\cell\row
\intbl{\b S7}\cell{Block address of simulation value}\cell\row
\intbl{\b S8}\cell{Simulation enable}\cell\row
\intbl{\b S9}\cell{Status error inhibit}\cell\row
\intbl{\b S10}\cell{HSOE enable}\cell\row
\intbl{\b S11}\cell{HSOE buffer size}\cell\row
\intbl{\b S12}\cell{HSOE maximum events}\cell\row
\intbl{\b S13}\cell{HSOE event time interval}\cell\row
\intbl{\b S14}\cell{HSOE off-scan time interval}\cell\row
\intbl{\b S15}\cell{32-character user scratch area}\cell\row
\intbl{\b S16}\cell{Reserved for future use}\cell\row
\intbl{\b S17}\cell{Spare}\cell\row
\intbl{\b S18}\cell{Spare}\cell\row
\intbl{\b S19}\cell{Spare}\cell\row
\intbl{\b S20}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Input value with quality}\cell\row\par
#225
\intbl{\b S1}\cell{32-character channel label}\cell\row
\intbl{\b S2}\cell{Block address of value to be output}\cell\row
\intbl{\b S3}\cell{Alarm state, non-normal state}\cell\row
\intbl{\b S4}\cell{Default state on stall}\cell\row
\intbl{\b S5}\cell{Readback enable}\cell\row
\intbl{\b S6}\cell{Normal output/undefined}\cell\row
\intbl{\b S7}\cell{Override value}\cell\row
\intbl{\b S8}\cell{Override enable}\cell\row
\intbl{\b S9}\cell{Block address of simulation value}\cell\row
\intbl{\b S10}\cell{Simulation enable}\cell\row
\intbl{\b S11}\cell{Status error inhibit}\cell\row
\intbl{\b S12}\cell{32-character user scratch area}\cell\row
\intbl{\b S13}\cell{Reserved for future use}\cell\row
\intbl{\b S14}\cell{Spare}\cell\row
\intbl{\b S15}\cell{Spare}\cell\row
\intbl{\b S16}\cell{Spare}\cell\row
\intbl{\b S17}\cell{Spare}\cell\row
\intbl{\b S18}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output value with quality}\cell\row\par
#226
\intbl{\b S1}\cell{Block address of Harmony I/O function code to test}\cell\row
\intbl{\b S2}\cell{Status condition 1}\cell\row
\intbl{\b S3}\cell{Status condition 2}\cell\row
\intbl{\b S4}\cell{Status condition 3}\cell\row
\intbl{\b S5}\cell{Status condition 4}\cell\row
\intbl{\b S6}\cell{Spare}\cell\row
\intbl{\b S7}\cell{Spare}\cell\row
\intbl{\b S8}\cell{Spare}\cell\row
\intbl{\b S9}\cell{Spare}\cell\row
\intbl{\b S10}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Result of status conditions 1 through 4: (0=false 1=true)}\cell\row\par
#227
\intbl{\b S1}\cell{32-character device label}\cell\row
\intbl{\b S2}\cell{Harmony communication block configuration parameters}\cell\row
\intbl{\b S3}\cell{Block address of first foreign device definition for communcation port 1}\cell\row
\intbl{\b S4}\cell{Communcation port 1 configuration parameters}\cell\row
\intbl{\b S5}\cell{Block address of first foreign device definition for communication port 2}\cell\row
\intbl{\b S6}\cell{Communication port 2 configuration parameters}\cell\row
\intbl{\b S7}\cell{Block address of first foreign device definition for communication port 3}\cell\row
\intbl{\b S8}\cell{Communication port 3 configuration parameters}\cell\row
\intbl{\b S9}\cell{Block address of first foreign device definition for communication port 4}\cell\row
\intbl{\b S10}\cell{Communication port 4 configuration parameters}\cell\row
\intbl{\b S11}\cell{Block address of override/status error inhibit/simulation permit}\cell\row
\intbl{\b S12}\cell{Device status error inhibit}\cell\row
\intbl{\b S13}\cell{Redundant gateway expected}\cell\row
\intbl{\b S15}\cell{NVM buffer size}\cell\row
\intbl{\b S16}\cell{Block address of next HSOE gateway FC 227 or device definition FC 221}\cell\row
\intbl{\b S17}\cell{Spare block address}\cell\row
\intbl{\b S18}\cell{Spare real}\cell\row
\intbl{\b S19}\cell{Spare string}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Primary communication block status with quality}\cell\row\
\intbl{\b N+1}\cell{Bit}\cell{Backup communication block status with quality}\cell\row\
\intbl{\b N+2}\cell{Bit}\cell{Communication port 1 with quality}\cell\row\
\intbl{\b N+3}\cell{Bit}\cell{Communication port 2 with quality}\cell\row\
\intbl{\b N+4}\cell{Bit}\cell{Communication port 3 with quality}\cell\row\
\intbl{\b N+5}\cell{Bit}\cell{Communication port 4 with quality}\cell\row\
\intbl{\b N+6}\cell{Bit}\cell{Spare output with quality}\cell\row\
\intbl{\b N+7}\cell{Real}\cell{Reserved output with quality}\cell\row\par
#228
\intbl{\b S1}\cell{32-character device label}\cell\row
\intbl{\b S2}\cell{Foreign device configuration parameters}\cell\row
\intbl{\b S3}\cell{Block address of the next foreign device}\cell\row
\intbl{\b S4}\cell{Block address of first channel}\cell\row
\intbl{\b S5}\cell{Device status error inhibit}\cell\row
\intbl{\b S6}\cell{Spare block address}\cell\row
\intbl{\b S7}\cell{Spare string}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Primary communication block status with quality}\cell\row\
\intbl{\b N+1}\cell{Real}\cell{Reserve output with quality}\cell\row\par
#229
\intbl{\b S1}\cell{32-character channel label}\cell\row
\intbl{\b S2}\cell{Filtering / conversion type}\cell\row
\intbl{\b S3}\cell{Engineering units low value}\cell\row
\intbl{\b S4}\cell{Engineering units high value}\cell\row
\intbl{\b S5}\cell{Engineering units ID}\cell\row
\intbl{\b S6}\cell{High alarm limit value}\cell\row
\intbl{\b S7}\cell{Low alarm limit value}\cell\row
\intbl{\b S8}\cell{Significant change in EU}\cell\row
\intbl{\b S9}\cell{Alarm dead-band in EU}\cell\row
\intbl{\b S10}\cell{Expected channel low value in units (Hz, sec, cts)}\cell\row
\intbl{\b S11}\cell{Expected channel high value in units (Hz, sec, cts)}\cell\row
\intbl{\b S12}\cell{Engineering unit start value}\cell\row
\intbl{\b S13}\cell{Block address of reset}\cell\row
\intbl{\b S14}\cell{Block address of hold}\cell\row
\intbl{\b S15}\cell{Normal input / undefined - 0=normal, 1=undefined}\cell\row
\intbl{\b S16}\cell{Override value}\cell\row
\intbl{\b S17}\cell{Override enable - 0 disables override, 1 enables override}\cell\row
\intbl{\b S18}\cell{Block address of simulation value}\cell\row
\intbl{\b S19}\cell{Simulation enable - 0 disables simulation, 1 enables simulation}\cell\row
\intbl{\b S20}\cell{Status error inhibit - 0=no, 1=yes}\cell\row
\intbl{\b S21}\cell{Redundant input deviation limit}\cell\row
\intbl{\b S22}\cell{Reserved}\cell\row
\intbl{\b S23}\cell{Foreign device configuration parameters}\cell\row
\intbl{\b S24}\cell{Reserved}\cell\row
\intbl{\b S25}\cell{Block address of the next element of the foreign device}\cell\row
\intbl{\b S26}\cell{Spare integer}\cell\row
\intbl{\b S27}\cell{Spare real}\cell\row
\intbl{\b S28}\cell{Spare real}\cell\row
\intbl{\b S29}\cell{Spare real}\cell\row
\intbl{\b S30}\cell{Spare real}\cell\row
\intbl{\b S31}\cell{Spare integer}\cell\row
\intbl{\b S32}\cell{Spare integer}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Pulse input value in EUs with quality}\cell\row\
#230
\intbl{\b S1}\cell{Analog input definition 1}\cell\row
\intbl{\b S2}\cell{Analog input definition 2}\cell\row
\intbl{\b S3}\cell{Analog input definition 3}\cell\row
\intbl{\b S4}\cell{Analog input definition 4}\cell\row
\intbl{\b S5}\cell{Analog output 1}\cell\row
\intbl{\b S6}\cell{Analog output 2}\cell\row
\intbl{\b S7}\cell{Digital output 1}\cell\row
\intbl{\b S8}\cell{Digital output 2}\cell\row
\intbl{\b S9}\cell{Digital output 3}\cell\row
\intbl{\b S10}\cell{Digital output 4}\cell\row
\intbl{\b S11}\cell{Pulse input}\cell\row
\intbl{\b S12}\cell{Failure action (0=trip controller 1=continue)}\cell\row
\intbl{\b S13}\cell{Spare real input}\cell\row
\intbl{\b S14}\cell{Spare parameter}\cell\row
\intbl{\b S15}\cell{Spare parameter}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 100}\cell{Real}\cell{Output is value of analog input 1 with quality}\cell\row
\intbl{\b 101}\cell{Real}\cell{Output is value of analog input 2 with quality}\cell\row
\intbl{\b 102}\cell{Real}\cell{Output is value of analog input 3 with quality}\cell\row
\intbl{\b 103}\cell{Real}\cell{Output is value of analog input 4 with quality}\cell\row
\intbl{\b 104}\cell{Real}\cell{Output is value of analog output 1 with quality}\cell\row
\intbl{\b 105}\cell{Real}\cell{Output is value of analog output 2 with quality}\cell\row
\intbl{\b 106}\cell{Bit}\cell{Output is value of digital input 1 with quality}\cell\row
\intbl{\b 107}\cell{Bit}\cell{Output is value of digital input 2 with quality}\cell\row
\intbl{\b 108}\cell{Bit}\cell{Output is value of digital input 3 with quality}\cell\row
\intbl{\b 109}\cell{Bit}\cell{Output is value of digital output 1 with quality}\cell\row
\intbl{\b 110}\cell{Bit}\cell{Output is value of digital output 2 with quality}\cell\row
\intbl{\b 111}\cell{Bit}\cell{Output is value of digital output 3 with quality}\cell\row
\intbl{\b 112}\cell{Bit}\cell{Output is value of digital output 4 with quality}\cell\row
\intbl{\b 113}\cell{Real}\cell{Output is value of pulse input with quality}\cell\row
\intbl{\b 114}\cell{Bit}\cell{Status: 0 - good, 1 - bad}\cell\row
\intbl{\b 115}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 116}\cell{Real}\cell{Reserved}\cell\row\par
#231
\intbl{\b S1}\cell{Loop 1 manual/auto station}\cell\row
\intbl{\b S2}\cell{Loop 2 manual/auto station}\cell\row
\intbl{\b S3}\cell{General purpose alarm number 1}\cell\row
\intbl{\b S4}\cell{General purpose alarm number 2}\cell\row
\intbl{\b S5}\cell{General purpose alarm number 3}\cell\row
\intbl{\b S6}\cell{General purpose alarm number 4}\cell\row
\intbl{\b S7}\cell{Auxiliary input 1}\cell\row
\intbl{\b S8}\cell{Auxiliary input 2}\cell\row
\intbl{\b S9}\cell{External alarm 1}\cell\row
\intbl{\b S10}\cell{External alarm 2}\cell\row
\intbl{\b S11}\cell{First ASCII string descriptor block}\cell\row
\intbl{\b S12}\cell{Digital output 1 output override permissive}\cell\row
\intbl{\b S13}\cell{Digital output 2 output override permissive}\cell\row
\intbl{\b S14}\cell{Digital output 3 output override permissive}\cell\row
\intbl{\b S15}\cell{Digital output 4 output override permissive}\cell\row
\intbl{\b S16}\cell{Default mode of outputs (0=manual 1=auto)}\cell\row
\intbl{\b S17}\cell{Spare real input}\cell\row
\intbl{\b S18}\cell{Spare parameter}\cell\row
\intbl{\b S19}\cell{Spare parameter}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b 900}\cell{Bit}\cell{Output indicates alarm status}\cell\row
\intbl{\b 901}\cell{Bit}\cell{Output indicates alarm acknowledge key}\cell\row
\intbl{\b 902}\cell{Bit}\cell{Output is value of loop 1 faceplate switch}\cell\row
\intbl{\b 903}\cell{Bit}\cell{Output is value of loop 2 faceplate switch}\cell\row
\intbl{\b 904}\cell{Bit}\cell{Output is value of auxiliary switch 1}\cell\row
\intbl{\b 905}\cell{Bit}\cell{Output is value of auxiliary switch 2}\cell\row
\intbl{\b 906}\cell{Bit}\cell{Output is value of auxiliary switch 3}\cell\row
\intbl{\b 907}\cell{Bit}\cell{Output is value of auxiliary switch 4}\cell\row
\intbl{\b 908}\cell{Bit}\cell{Auto/manual mode of digital output 1}\cell\row
\intbl{\b 909}\cell{Bit}\cell{Auto/manual mode of digital output 2}\cell\row
\intbl{\b 910}\cell{Bit}\cell{Auto/manual mode of digital output 3}\cell\row
\intbl{\b 911}\cell{Bit}\cell{Auto/manual mode of digital output 4}\cell\row
\intbl{\b 912}\cell{Real}\cell{Reserved}\cell\row
\intbl{\b 913}\cell{Real}\cell{Reserved}\cell\row\par
#232
#233
#234
#235
#236
#237
#238
#239
#240
#241
\intbl{\b S1}\cell{Slave address of set module}\cell\row
\intbl{\b S2}\cell{Number of events}\cell\row
\intbl{\b S3}\cell{First input handler}\cell\row
\intbl{\b S4}\cell{Spare integer parameter}\cell\row
\intbl{\b S5}\cell{Spare real parameter}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Events logged: (with quality and alarm) 0 - no, 1 - yes}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Output is value of module status: 0 - good, 1 - bad }\cell\row
\par
#242
\intbl{\b S1}\cell{Slave address of SED or SET module}\cell\row
\intbl{\b S2}\cell{Next digital event interface (FC 242)}\cell\row
\intbl{\b S3}\cell{Debounce filter time (msecs)}\cell\row
\intbl{\b S4}\cell{Input scan mask}\cell\row
\intbl{\b S5}\cell{TON - channel 0}\cell\row
\intbl{\b S6}\cell{TOFF - channel 0}\cell\row
\intbl{\b S7}\cell{TON - channel 1}\cell\row
\intbl{\b S8}\cell{TOFF - channel 1}\cell\row
\intbl{\b S9}\cell{TON - channel 2}\cell\row
\intbl{\b S10}\cell{TOFF - channel 2}\cell\row
\intbl{\b S11}\cell{TON - channel 3}\cell\row
\intbl{\b S12}\cell{TOFF - channel 3}\cell\row
\intbl{\b S13}\cell{TON - channel 4}\cell\row
\intbl{\b S14}\cell{TOFF - channel 4}\cell\row
\intbl{\b S15}\cell{TON - channel 5}\cell\row
\intbl{\b S16}\cell{TOFF - channel 5}\cell\row
\intbl{\b S17}\cell{TON - channel 6}\cell\row
\intbl{\b S18}\cell{TOFF - channel 6}\cell\row
\intbl{\b S19}\cell{TON - channel 7}\cell\row
\intbl{\b S20}\cell{TOFF - channel 7}\cell\row
\intbl{\b S21}\cell{TON - channel 8}\cell\row
\intbl{\b S22}\cell{TOFF - channel 8}\cell\row
\intbl{\b S23}\cell{TON - channel 9}\cell\row
\intbl{\b S24}\cell{TOFF - channel 9}\cell\row
\intbl{\b S25}\cell{TON - channel 10}\cell\row
\intbl{\b S26}\cell{TOFF - channel 10}\cell\row
\intbl{\b S27}\cell{TON - channel 11}\cell\row
\intbl{\b S28}\cell{TOFF - channel 11}\cell\row
\intbl{\b S29}\cell{TON - channel 12}\cell\row
\intbl{\b S30}\cell{TOFF - channel 12}\cell\row
\intbl{\b S31}\cell{TON - channel 13}\cell\row
\intbl{\b S32}\cell{TOFF - channel 13}\cell\row
\intbl{\b S33}\cell{TON - channel 14}\cell\row
\intbl{\b S34}\cell{TOFF - channel 14}\cell\row
\intbl{\b S35}\cell{TON - channel 15}\cell\row
\intbl{\b S36}\cell{TOFF - channel 15}\cell\row
\intbl{\b S37}\cell{Spare}\cell\row
\intbl{\b S38}\cell{Spare}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Bit}\cell{Output 1 with quality}\cell\row
\intbl{\b N+1}\cell{Bit}\cell{Output 2 with quality}\cell\row
\intbl{\b N+2}\cell{Bit}\cell{Output 3 with quality}\cell\row
\intbl{\b N+3}\cell{Bit}\cell{Output 4 with quality}\cell\row
\intbl{\b N+4}\cell{Bit}\cell{Output 5 with quality}\cell\row
\intbl{\b N+5}\cell{Bit}\cell{Output 6 with quality}\cell\row
\intbl{\b N+6}\cell{Bit}\cell{Output 7 with quality}\cell\row
\intbl{\b N+7}\cell{Bit}\cell{Output 8 with quality}\cell\row
\intbl{\b N+8}\cell{Bit}\cell{Output 9 with quality}\cell\row
\intbl{\b N+9}\cell{Bit}\cell{Output 10 with quality}\cell\row
\intbl{\b N+10}\cell{Bit}\cell{Output 11 with quality}\cell\row
\intbl{\b N+11}\cell{Bit}\cell{Output 12 with quality}\cell\row
\intbl{\b N+12}\cell{Bit}\cell{Output 13 with quality}\cell\row
\intbl{\b N+13}\cell{Bit}\cell{Output 14 with quality}\cell\row
\intbl{\b N+14}\cell{Bit}\cell{Output 15 with quality}\cell\row
\intbl{\b N+15}\cell{Bit}\cell{Output 16 with quality}\cell\row
\intbl{\b N+16}\cell{Bit}\cell{Output is value of module status: 0 - good, 1 - bad }\cell\row
\par
#243
\intbl{\b S1}\cell{Maximum number of pre-trigger events}\cell\row
\intbl{\b S2}\cell{Maximum number of post-trigger events}\cell\row
\intbl{\b S3}\cell{Length (seconds) of post-trigger period}\cell\row
\intbl{\b S4}\cell{Longest time interval between two consecutive events}\cell\row
\intbl{\b S5}\cell{Maximum delay (seconds) in receiving events from Harmony controller}\cell\row
\intbl{\b S6}\cell{Age of event data in seconds before discarding}\cell\row
\intbl{\b S7}\cell{Block number of first MFP-SEM interface definition FC 244}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{N/A}\cell{Not used}\cell\row\par
#244
\intbl{\b S1}\cell{Loop address}\cell\row
\intbl{\b S2}\cell{PCU address}\cell\row
\intbl{\b S3}\cell{Module address}\cell\row
\intbl{\b S4}\cell{Block number of SEM-MFP interface FC 241}\cell\row
\intbl{\b S5}\cell{Block number of next MFP-SEM interface FC 244}\cell\row
\intbl{\b S6}\cell{Block number of first SED-SEM interface FC 245}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{N/A}\cell{Not used}\cell\row\par
#245
\intbl{\b S1}\cell{Slave address}\cell\row
\intbl{\b S2}\cell{Next SED-SEM interface FC 245}\cell\row
\intbl{\b S3}\cell{Characteristics of channel 0 input}\cell\row
\intbl{\b S4}\cell{Characteristics of channel 1 input}\cell\row
\intbl{\b S5}\cell{Characteristics of channel 2 input}\cell\row
\intbl{\b S6}\cell{Characteristics of channel 3 input}\cell\row
\intbl{\b S7}\cell{Characteristics of channel 4 input}\cell\row
\intbl{\b S8}\cell{Characteristics of channel 5 input}\cell\row
\intbl{\b S9}\cell{Characteristics of channel 6 input}\cell\row
\intbl{\b S10}\cell{Characteristics of channel 7 input}\cell\row
\intbl{\b S11}\cell{Characteristics of channel 8 input}\cell\row
\intbl{\b S12}\cell{Characteristics of channel 9 input}\cell\row
\intbl{\b S13}\cell{Characteristics of channel 10 input}\cell\row
\intbl{\b S14}\cell{Characteristics of channel 11 input}\cell\row
\intbl{\b S15}\cell{Characteristics of channel 12 input}\cell\row
\intbl{\b S16}\cell{Characteristics of channel 13 input}\cell\row
\intbl{\b S17}\cell{Characteristics of channel 14 input}\cell\row
\intbl{\b S18}\cell{Characteristics of channel 15 input}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{N/A}\cell{Not used}\cell\row\par
#246
\intbl{\b S1}\cell{Operation/operand 1}\cell\row
\intbl{\b S2}\cell{Operation/operand 2}\cell\row
\intbl{\b S3}\cell{Operation/operand 3}\cell\row
\intbl{\b S4}\cell{Operation/operand 4}\cell\row
\intbl{\b S5}\cell{Operation/operand 5}\cell\row
\intbl{\b S6}\cell{Operation/operand 6}\cell\row
\intbl{\b S7}\cell{Operation/operand 7}\cell\row
\intbl{\b S8}\cell{Operation/operand 8}\cell\row
\intbl{\b S9}\cell{Operation/operand 9}\cell\row
\intbl{\b S10}\cell{Operation/operand 10}\cell\row
\intbl{\b S11}\cell{Operation/operand 11}\cell\row
\intbl{\b S12}\cell{Operation/operand 12}\cell\row
\intbl{\b S13}\cell{Operation/operand 13}\cell\row
\intbl{\b S14}\cell{Operation/operand 14}\cell\row
\intbl{\b S15}\cell{Operation/operand 15}\cell\row
\intbl{\b S16}\cell{Operation/operand 16}\cell\row
\intbl{\b S17}\cell{Operation/operand 17}\cell\row
\intbl{\b S18}\cell{Operation/operand 18}\cell\row
\intbl{\b S19}\cell{Operation/operand 19}\cell\row
\intbl{\b S20}\cell{Operation/operand 20}\cell\row
\intbl{\b S21}\cell{Operation/operand 21}\cell\row
\intbl{\b S22}\cell{Operation/operand 22}\cell\row
\intbl{\b S23}\cell{Operation/operand 23}\cell\row
\intbl{\b S24}\cell{Operation/operand 24}\cell\row
\intbl{\b S25}\cell{Operation/operand 25}\cell\row
\intbl{\b S26}\cell{Operation/operand 26}\cell\row
\intbl{\b S27}\cell{Operation/operand 27}\cell\row
\intbl{\b S28}\cell{Operation/operand 28}\cell\row
\intbl{\b S29}\cell{Operation/operand 29}\cell\row
\intbl{\b S30}\cell{Operation/operand 30}\cell\row
\intbl{\b S31}\cell{Operation/operand 31}\cell\row
\intbl{\b S32}\cell{Operation/operand 32}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{N/A}\cell{Not used}\cell\row\par
#247
\intbl{\b S1}\cell{Module access}\cell\row
\intbl{\b S2}\cell{Block address of next CMM channel}\cell\row
\intbl{\b S3}\cell{Module channel input number}\cell\row
\intbl{\b S4}\cell{Channel type 1-9}\cell\row
\intbl{\b S5}\cell{Probe type 0-7}\cell\row
\intbl{\b S6}\cell{Integration 0-3}\cell\row
\intbl{\b S7}\cell{Block output select}\cell\row
\intbl{\b S8}\cell{English/metric EU}\cell\row
\intbl{\b S9}\cell{Block address of alert enable (Boolean input)}\cell\row
\intbl{\b S10}\cell{Block address of danger enable (Boolean input)}\cell\row
\intbl{\b S11}\cell{Block address of set alert relay (Boolean input)}\cell\row
\intbl{\b S12}\cell{Block address of set danger relay (Boolean input)}\cell\row
\intbl{\b S13}\cell{Normal alert relay state}\cell\row
\intbl{\b S14}\cell{Normal danger relay state}\cell\row
\intbl{\b S15}\cell{Vote enable}\cell\row
\intbl{\b S16}\cell{Block address of set null position voltage (Boolean input)}\cell\row
\intbl{\b S17}\cell{Block address of filter low cutoff frequency (real input)}\cell\row
\intbl{\b S18}\cell{Block address of filter high cutoff frequency (real input)}\cell\row
\intbl{\b S19}\cell{Block address of waverform capture (Boolean input)}\cell\row
\intbl{\b S20}\cell{Block address of run-up capture (Boolean input)}\cell\row
\intbl{\b S21}\cell{Block address of run-down capture (Boolean input)}\cell\row
\intbl{\b S22}\cell{Block address of event active (Boolean input)}\cell\row
\intbl{\b S23}\cell{Block address of engineering unit high danger level (real input)}\cell\row
\intbl{\b S24}\cell{Block address of engineering unit high alert level (real input)}\cell\row
\intbl{\b S25}\cell{Block address of engineering unit low alert level (real input)}\cell\row
\intbl{\b S26}\cell{Block address of engineering unit low danger level (real input)}\cell\row
\intbl{\b S27}\cell{Block address of alert delay (seconds)(real input)}\cell\row
\intbl{\b S28}\cell{Block address of danger delay (seconds)(real input)}\cell\row
\intbl{\b S29}\cell{Block address of shaft rotational direction (Boolean input)}\cell\row
\intbl{\b S30}\cell{Angular position of event marker probe}\cell\row
\intbl{\b S31}\cell{Angular position of event marker probe}\cell\row
\intbl{\b S32}\cell{Point ID}\cell\row
\intbl{\b S33}\cell{IP address one}\cell\row
\intbl{\b S34}\cell{IP address two}\cell\row
\intbl{\b S35}\cell{IP address three}\cell\row
\intbl{\b S36}\cell{IP address four}\cell\row
\intbl{\b S37}\cell{Sub-net mask one}\cell\row
\intbl{\b S38}\cell{Sub-net mask two}\cell\row
\intbl{\b S39}\cell{Sub-net mask three}\cell\row
\intbl{\b S40}\cell{Sub-net mask four}\cell\row
\intbl{\b S41}\cell{Spare integer parameter}\cell\row
\intbl{\b S42}\cell{Spare integer parameter}\cell\row
\intbl{\b S43}\cell{Spare block address (Boolean input)}\cell\row
\intbl{\b S44}\cell{Spare block address (Boolean input)}\cell\row
\intbl{\b S45}\cell{Spare block address (real input)}\cell\row
\intbl{\b S46}\cell{Spare block address (real input)}\cell\row
\intbl{\b S47}\cell{Block address of non-linear correction (real input)}\cell\row
\intbl{\b S48}\cell{Probe sensitivity (millivolts/EU)}\cell\row
\intbl{\b S49}\cell{Null position in engineering units}\cell\row
\intbl{\b S50}\cell{Null position voltage (used for channel types 2, 4 only)}\cell\row
\intbl{\b S51}\cell{High probe failure voltage}\cell\row
\intbl{\b S52}\cell{High probe failure voltage}\cell\row
\intbl{\b S53}\cell{Spare real parameter}\cell\row
\intbl{\b S54}\cell{Spare real parameter}\cell\row
\intbl{\b S55}\cell{Spare real parameter}\cell\row
\par\sb120\li120\sa120{\fs28\b Outputs}\par\pard
\trowd\trgaph240\cellx960\cellx1920\cellx10080
\intbl{\b Block}\cell{\b Type}\cell{\b Description}\cell\row
\intbl{\b N}\cell{Real}\cell{Output in engineering units, quality}\cell\row\
\intbl{\b N+1}\cell{Real}\cell{Average (DC/gap) voltage}\cell\row\
\intbl{\b N+2}\cell{Real}\cell{Speed}\cell\row\
\intbl{\b N+3}\cell{Real}\cell{First order vibration in EU (vibration only)}\cell\row\
\intbl{\b N+4}\cell{Real}\cell{First order phase angle (degrees) (vibration only)}\cell\row\
\intbl{\b N+5}\cell{Real}\cell{Second order vibration in EU (vibration only)}\cell\row\
\intbl{\b N+6}\cell{Real}\cell{Second order phase angle (degrees)(vibration only)}\cell\row\
\intbl{\b N+7}\cell{Real}\cell{Third order vibration in EU (vibration only)}\cell\row\
\intbl{\b N+8}\cell{Real}\cell{Third order phase angle (degrees)(vibration only)}\cell\row\
\intbl{\b N+9}\cell{Real}\cell{Not first order vibration (not 1X)(vibration only)}\cell\row\
\intbl{\b N+10}\cell{Bit}\cell{Alert (0=OK; 1=Alarm)}\cell\row\
\intbl{\b N+11}\cell{Bit}\cell{Danger (0=OK; 1= Alarm)}\cell\row\
\intbl{\b N+12}\cell{Bit}\cell{Module status (0=good; 1= bad)}\cell\row\par
#248
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